wiki:Other/Summer/2017/FPGAEncryption

Design of a pseudo-language for FPGA programming

Table of Contents

  1. 2017 WINLAB Summer Internship
    1. Projects
  2. Drone Communication Analysis
    1. Introduction
    2. Background
    3. Tools Used
    4. Presentations
    5. Team Members
    1. Design of a pseudo-language for FPGA programming
      1. Mission
      2. Presentations
      3. The Team
  4. Mobility First : Multihoming Extension
    1. Introduction
      1. Mobility First
      2. Multihoming
    2. Mission
    3. Implementation
    4. Results
    5. Presentations
    6. People
  5. External References
    1. Quit Smoking Application
  7. SDR Smart Modem
    1. Introduction
    2. Background
    3. Tools Used
    4. Presentations
    5. The Team
    6. References

Mission

The purpose of this project is to lower the entry level for software engineers to get into writing synthesizable Verilog code by introducing a middle language for ease of use. By introducing a compiler that takes code written in a language based off of BASIC, and compiles it to a verilog switch block, the burden of many of the hardware constraints in FPGAs are taken off of the programmer.

Presentations

Week 1
Week 2
Week 3
Week 4
Week 5
Week 7
Week 8
Week 9
Week 10
Week 11

The Team
Nicholas Lurski
Electrical and Computer Engineering

Rutgers University		 Zarir Hamza
High School

Middlesex County Academy for Science,
Mathematics and Engineering Technologies


Project guided by Dr. Richard Martin.
Last modified 7 years ago Last modified on Aug 2, 2017, 3:36:45 PM

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