Design of a pseudo-language for FPGA programming


The purpose of this project is to lower the entry level for software engineers to get into writing synthesizable Verilog code by introducing a middle language for ease of use. By introducing a compiler that takes code written in a language based off of BASIC, and compiles it to a verilog switch block, the burden of many of the hardware constraints in FPGAs are taken off of the programmer.


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Week 11

The Team

Nicholas Lurski
Electrical and Computer Engineering

Rutgers University
Zarir Hamza
High School

Middlesex County Academy for Science,
Mathematics and Engineering Technologies

Project guided by Dr. Richard Martin.
Last modified 3 years ago Last modified on Aug 2, 2017, 3:36:45 PM

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