== Design of a pseudo-language for FPGA programming== [[TOC(Other/Summer/2017*, depth=4)]] === Mission === The purpose of this project is to lower the entry level for software engineers to get into writing synthesizable Verilog code by introducing a middle language for ease of use. By introducing a compiler that takes code written in a language based off of BASIC, and compiles it to a verilog switch block, the burden of many of the hardware constraints in FPGAs are taken off of the programmer. === Presentations === {{{ #!html Week 1
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}}} === The Team === {{{ #!html
Nicholas Lurski
Electrical and Computer Engineering

Rutgers University
Zarir Hamza
High School

Middlesex County Academy for Science,
Mathematics and Engineering Technologies


Project guided by Dr. Richard Martin.
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