Changes between Version 5 and Version 6 of Other/Summer/2017/FPGAEncryption


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Timestamp:
Jul 19, 2017, 2:08:56 AM (7 years ago)
Author:
nlurski
Comment:

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  • Other/Summer/2017/FPGAEncryption

    v5 v6  
    1 == Porting the RC5 Encryption Scheme to Synthesizable Verilog ==
     1== Design of a pseudo-language for FPGA programming==
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    33[[TOC(Other/Summer/2017*, depth=4)]]
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    77=== Mission  ===
    8 The RC5 encryption scheme (Rivest's Cypher) will be ported to an FPGA using synthesizable verilog. The benefit of this would be scalability of encryption.
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    12 === Background  ===
    13 ==== Rivest's Cypher Encryption ====
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    21 === Progress ===
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     8Designing a psuedo-language based on the BASIC programming language, in order to lower the entry point for FPGA programming. The RC5 encryption scheme (Rivest's Cypher) will be ported to an FPGA using synthesizable verilog. The benefit of this would be scalability of encryption. This motive for porting the RC5 scheme using our new language is to prove the efficacy of the new language for writing FPGA programs
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