Changes between Version 1 and Version 2 of Other/Summer/2017/FPGAEncryption


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Timestamp:
Jun 5, 2017, 6:16:44 PM (7 years ago)
Author:
nlurski
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  • Other/Summer/2017/FPGAEncryption

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    1 Placeholder text
     1== Porting the RC5 Encryption Scheme to Synthesizable Verilog ==
     2
     3[[TOC(Other/Summer/2017*, depth=4)]]
     4
     5
     6
     7=== Mission  ===
     8The RC5 encryption scheme (Rivest's Cypher) will be ported to an FPGA using synthesizable verilog. The benefit of this would be scalability of encryption.
     9
     10
     11
     12=== Background  ===
     13==== Rivest's Cypher Encryption ====
     14
     15
     16=== Project Github  ===
     17
     18
     19
     20
     21=== Progress ===
     22 
     23
     24
     25=== Presentations  ===
     26 {{{
     27#!html
     28
     29<a href = ""> Week 2 </a>
     30<br>
     31<br>
     32
     33<a href = ""> Week 3 </a>
     34<br>
     35<br>
     36
     37
     38}}}
     39
     40=== The Team ===
     41
     42 {{{
     43#!html
     44
     45<center>
     46<table cellpadding=10>
     47  <tr>
     48    <td><center><img src="http://www.orbit-lab.org/raw-attachment/wiki/Other/Summer/2016/SDRSpectrumDrone/nick.jpg" height=300></center></td>
     49  </tr>
     50  <tr>
     51    <td align='center'><b>Nicholas Lurski</b><br>Electrical and Computer Engineering<br><br><i>Rutgers University</i></td>
     52  </tr>   
     53</table>
     54
     55   
     56</table>
     57
     58
     59<br><br>Project guided by Dr. Richard Martin.
     60
     61</center>
     62}}}