Nutaq - PicoSDR start-up and configuration
Table of Contents
- SDR Tutorials
- Multi Channel Sample Processing & Visualization
- Plot the IQ Constellation of received signal
Demonstrate configuring PicoSDR and launching demo application that utilizes Perseus carrier board for RX/TX.
Before you can access the testbed, you need to make a reservation and get it approved by the reservation service?. After receiving the reservation's confirmation (approval) email, load the ubuntu-14-04-64bit-sdr.ndz on the node. Once loading is finished turn the node on. For this example we'll use node1-12 which is a PicoSDR.
ssh email@example.com omf load -i ubuntu-14-04-64bit-sdr.ndz -t node1-12 omf tell -a on -t node1-12
Once the node1-12 is up, ssh into the node1-12 (which is the PicoSDR's embedded PC) and configure the eth2 interface
ifconfig eth2 192.168.0.100 up
Verify connection to Perseus carrier board:
Use a command line interface to load the Perseus carrier board with an FPGA bitsteam - for this example we'll use the "/opt/Nutaq/ADP6/ADP_MicroTCA/sdk/fpga/bin/GNURadio_Radio420_PCIe_sx315.bit":
cd /opt/Nutaq/ADP6/ADP_MicroTCA/sdk/bin python adp_cli.py connect 192.168.0.101 fpgaflash 1 ‘/opt/Nutaq/ADP6/ADP_MicroTCA/sdk/fpga/bin/GNURadio_Radio420_PCIe_sx315.bit’ reboot
The PicoSDR2x2E block diagram shown below describes how all the peripherals interconnect with the embedded CPU (Quad-Core CPU) and FPGA (Virtex-6).
Since GNURadio_Radio420_PCIe_sx315.bit uses the PCI Express Bus to interface between the embedded PC and carrier board's FPGA (Virtex-6), install the PCI Express Driver on the embedded PC:
cd /opt/Nutaq/ADP6/ADP_MicroTCA/sdk/PCIe/driver/host sh make-modules.sh sh setonpc.sh
If the embedded PC is restarted then setonpc.sh must be excuted again
Launch demo scripts
Now the system is ready to build and run the demo application. Navigate to the demo project directory:
cd /opt/Nutaq/ADP6/ADP_MicroTCA/sdk/examples/perseus6010_radio420x_rtdex_record_playback/host/prj_linux sh build_demo.sh
Run the demo file:
Choose the appropriate option to run.
Choose the data path: - Type '0' to execute passthrough (data looped from ADC to DAC in the FPGA) - Type '1' to output DDS signal (generated in the FPGA) - Type '2' to execute a data record - Type '3' to execute a data playback - Type '4' to stream data to the host - Type '5' to stream data from the host
From here you can use a nearby USRP node on the grid for signal generation / verification. Please refer to this tutorial for instruction on using USRPs.