INFO exp: Progress(0/0/1): 10/10/10 min(n_1_1)/avg/max (78) - Timeout: 670 sec. INFO exp: Progress(0/0/1): 10/10/10 min(n_1_1)/avg/max (78) - Timeout: 660 sec. INFO exp: Progress(0/0/1): 20/20/20 min(n_1_1)/avg/max (78) - Timeout: 650 sec. INFO exp: Progress(0/0/1): 20/20/20 min(n_1_1)/avg/max (78) - Timeout: 640 sec. INFO exp: Progress(0/0/1): 20/20/20 min(n_1_1)/avg/max (78) - Timeout: 630 sec. INFO exp: Progress(0/0/1): 30/30/30 min(n_1_1)/avg/max (78) - Timeout: 620 sec. INFO exp: Progress(0/0/1): 30/30/30 min(n_1_1)/avg/max (78) - Timeout: 610 sec. INFO exp: Progress(0/0/1): 30/30/30 min(n_1_1)/avg/max (78) - Timeout: 600 sec. INFO exp: Progress(0/0/1): 40/40/40 min(n_1_1)/avg/max (78) - Timeout: 590 sec. INFO exp: Progress(0/0/1): 40/40/40 min(n_1_1)/avg/max (78) - Timeout: 580 sec. INFO exp: Progress(0/0/1): 40/40/40 min(n_1_1)/avg/max (78) - Timeout: 570 sec. INFO exp: Progress(0/0/1): 50/50/50 min(n_1_1)/avg/max (78) - Timeout: 560 sec. INFO exp: Progress(0/0/1): 50/50/50 min(n_1_1)/avg/max (78) - Timeout: 550 sec. INFO exp: Progress(0/0/1): 50/50/50 min(n_1_1)/avg/max (78) - Timeout: 540 sec. INFO exp: Progress(0/0/1): 60/60/60 min(n_1_1)/avg/max (78) - Timeout: 530 sec. INFO exp: Progress(0/0/1): 60/60/60 min(n_1_1)/avg/max (78) - Timeout: 520 sec. INFO exp: Progress(0/0/1): 60/60/60 min(n_1_1)/avg/max (78) - Timeout: 510 sec. INFO exp: Progress(0/0/1): 70/70/70 min(n_1_1)/avg/max (78) - Timeout: 500 sec. INFO exp: Progress(0/0/1): 70/70/70 min(n_1_1)/avg/max (78) - Timeout: 490 sec. INFO exp: Progress(0/0/1): 70/70/70 min(n_1_1)/avg/max (78) - Timeout: 480 sec. INFO exp: Progress(0/0/1): 80/80/80 min(n_1_1)/avg/max (78) - Timeout: 470 sec. INFO exp: Progress(0/0/1): 80/80/80 min(n_1_1)/avg/max (78) - Timeout: 460 sec. INFO exp: Progress(0/0/1): 80/80/80 min(n_1_1)/avg/max (78) - Timeout: 450 sec. INFO exp: Progress(0/0/1): 90/90/90 min(n_1_1)/avg/max (78) - Timeout: 440 sec. INFO exp: Progress(0/0/1): 90/90/90 min(n_1_1)/avg/max (78) - Timeout: 430 sec. INFO exp: Progress(0/0/1): 90/90/90 min(n_1_1)/avg/max (78) - Timeout: 420 sec. INFO exp: Progress(1/0/1): 100/100/100 min()/avg/max (78) - Timeout: 410 sec. INFO exp: ----------------------------- INFO exp: Imaging Process Done INFO exp: - 1 node(s) successfully imaged - See the topology file: '/tmp/sb9.orbit-lab.org_2011_03_10_09_21_13_topo_active.rb' INFO exp: ----------------------------- INFO Experiment: DONE! INFO NodeHandler: Shutting down experiment, please wait... INFO NodeHandler: Shutdown flag is set - Turning Off the resources INFO run: Experiment sb9.orbit-lab.org_2011_03_10_09_21_13 finished after 6:31 nkiran@console:~$ omf stat INFO NodeHandler: init OMF Experiment Controller 5.2.408 ----------------------------------------------- INFO Topology: Loading topology 'system:topo:all'. Testbed : sb9.orbit-lab.org Node n_1_1 - State: POWEROFF Node n_1_2 - State: POWERON Node n_1_3 - State: POWERON Node n_1_4 - State: POWERON Node n_1_5 - State: POWEROFF Node n_1_6 - State: POWEROFF Node n_1_7 - State: NODE NOT AVAILABLE Node n_1_8 - State: NODE NOT AVAILABLE ----------------------------------------------- nkiran@console:~$ omf stattell on "1,1" INFO NodeHandler: init OMF Experiment Controller 5.2.408 --------------------------------------------------- Testbed : sb9.orbit-lab.org - Command: on Node n_1_1 - Ok --------------------------------------------------- nkiran@console:~$ ssh 1 ssh: connect to host node1-1 port 22: No route to host nkiran@console:~$ ssh 1 Last login: Wed Mar 9 20:17:28 2011 from consolec.sb9.orbit-lab.org ]0;root@node1-1.sb9.orbit-lab.org: ~root@node1-1:~# ifconfig -a control Link encap:Ethernet HWaddr 00:15:17:d6:da:4b inet addr:10.19.1.1 Bcast:10.19.255.255 Mask:255.255.0.0 inet6 addr: fe80::215:17ff:fed6:da4b/64 Scope:Link UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1 RX packets:65 errors:0 dropped:0 overruns:0 frame:0 TX packets:76 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:10638 (10.6 KB) TX bytes:11396 (11.3 KB) Memory:febe0000-fec00000 exp0 Link encap:Ethernet HWaddr 00:15:17:d6:da:4a BROADCAST MULTICAST MTU:1500 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B) Memory:feb80000-feba0000 lo Link encap:Local Loopback inet addr:127.0.0.1 Mask:255.0.0.0 inet6 addr: ::1/128 Scope:Host UP LOOPBACK RUNNING MTU:16436 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:0 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B) nf2c0 Link encap:Ethernet HWaddr 00:4e:46:32:43:00 BROADCAST MULTICAST MTU:1500 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B) Interrupt:16 nf2c1 Link encap:Ethernet HWaddr 00:4e:46:32:43:01 BROADCAST MULTICAST MTU:1500 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B) Interrupt:16 nf2c2 Link encap:Ethernet HWaddr 00:4e:46:32:43:02 BROADCAST MULTICAST MTU:1500 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B) Interrupt:16 nf2c3 Link encap:Ethernet HWaddr 00:4e:46:32:43:03 BROADCAST MULTICAST MTU:1500 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B) Interrupt:16 ]0;root@node1-1.sb9.orbit-lab.org: ~root@node1-1:~# root@node1-1:~# ls omf-common-5.2_ubuntu2_all.deb ]0;root@node1-1.sb9.orbit-lab.org: ~root@node1-1:~# exit logout Connection to node1-1 closed. nkiran@console:~$ ssh 1n1e1t1f1p1g1a1@1 netfpga@node1-1's password: Last login: Wed Mar 9 18:24:12 2011 from consolec.sb9.orbit-lab.org ]0;netfpga@node1-1: ~netfpga@node1-1:~$ clls netfpga pkgs ]0;netfpga@node1-1: ~netfpga@node1-1:~$ clear ]0;netfpga@node1-1: ~netfpga@node1-1:~$ ls netfpga pkgs ]0;netfpga@node1-1: ~netfpga@node1-1:~$ pwd /home/netfpga ]0;netfpga@node1-1: ~netfpga@node1-1:~$ ls netfpga pkgs ]0;netfpga@node1-1: ~netfpga@node1-1:~$ ]0;netfpga@node1-1: ~netfpga@node1-1:~$ /usr/local/sbin/cpci_reprogram.pl --all Error: /usr/local/sbin/cpci_reprogram.pl must be run as root at /usr/local/sbin/cpci_reprogram.pl line 36. ]0;netfpga@node1-1: ~netfpga@node1-1:~$ /usr/local/sbin/cpci_reprogram.pl --all[1@s[1@u[1@d[1@o[1@ Loading the CPCI Reprogrammer on NetFPGA 0 Loading the CPCI on NetFPGA 0 CPCI on NetFPGA 0 has been successfully reprogrammed ]0;netfpga@node1-1: ~netfpga@node1-1:~$ vi /usr/local/netfpga/vi /etc/rc.local [?1049h[?1h=[?12;25h[?12l[?25h[?25l"/etc/rc.local" [readonly] 14L, 306C[>c#!/bin/sh -e # # rc.local # # This script is executed at the end of each multiuser runlevel. # Make sure that the script will "exit 0" on success or any other # value on error. # # In order to enable or disable this script just change the execution # bits. # # By default this script does nothing. exit 0 ~ ~ ~ ~ ~ ~ ~ ~ ~ 1,1All[?12l[?25hP+q436f\P+q6b75\P+q6b64\P+q6b72\P+q6b6c\P+q2332\P+q2334\P+q2569\P+q2a37\P+q6b31\P+q6b32\[?25l#!/bin/sh -e # # rc.local # # This script is executed at the end of each multiuser runlevel. # Make sure that the script will "exit 0" on success or any other # value on error. # # In order to enable or disable this script just change the execution # bits. # # By default this script does nothing. exit 0 ~ ~ ~ ~ ~ ~ ~ ~ ~ 1,1All "/etc/rc.local" [readonly] 14L, 306C1,1All[?12l[?25hP+q6b33\[?25l[?12l[?25hP+q6b34\P+q6b35\P+q6b36\P+q6b37\P+q6b38\P+q6b39\P+q6b3b\P+q4631\P+q4632\P+q2531\P+q2638\P+q6b62\P+q6b49\P+q6b44\P+q6b68\P+q4037\P+q6b50\P+q6b4e\P+q4b31\P+q4b33\P+q4b34\P+q4b35\P+q6b42\[?25l2[?12l[?25h[?25l3[?12l[?25h[?25l4[?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l9[?12l[?25h[?25l10,1[?12l[?25h[?25l1[?12l[?25h[?25l2[?12l[?25h[?25l3,0-1[?12l[?25h[?25l4,1 [?12l[?25h[?25l3,0-1[?12l[?25h[?25l2,1 [?12l[?25h[?25lW10: Warning: Changing a readonly file-- INSERT --13,1Top13,1All[?12l[?25h[?25l13,0-1All[?12l[?25h[?25l:[?12l[?25hq[?25l[?12l[?25h![?25l[?12l[?25h [?25l[?1l>[?12l[?25h[?1049l]0;netfpga@node1-1: ~netfpga@node1-1:~$ vi /etc/rc.local [1@s[1@u[1@d[1@o[1@ [?1049h[?1h=[?12;25h[?12l[?25h[?25l"/etc/rc.local" 14L, 306C[>c#!/bin/sh -e # # rc.local # # This script is executed at the end of each multiuser runlevel. # Make sure that the script will "exit 0" on success or any other # value on error. # # In order to enable or disable this script just change the execution # bits. # # By default this script does nothing. exit 0 ~ ~ ~ ~ ~ ~ ~ ~ ~ 1,1All[?12l[?25hP+q436f\P+q6b75\P+q6b64\P+q6b72\P+q6b6c\P+q2332\P+q2334\P+q2569\P+q2a37\P+q6b31\P+q6b32\[?25l#!/bin/sh -e # # rc.local # # This script is executed at the end of each multiuser runlevel. # Make sure that the script will "exit 0" on success or any other # value on error. # # In order to enable or disable this script just change the execution # bits. # # By default this script does nothing. exit 0 ~ ~ ~ ~ ~ ~ ~ ~ ~ 1,1All "/etc/rc.local" 14L, 306C1,1All[?12l[?25hP+q6b33\[?25l[?12l[?25hP+q6b34\P+q6b35\P+q6b36\P+q6b37\P+q6b38\P+q6b39\P+q6b3b\P+q4631\P+q4632\P+q2531\P+q2638\P+q6b62\P+q6b49\P+q6b44\P+q6b68\P+q4037\P+q6b50\P+q6b4e\P+q4b31\P+q4b33\P+q4b34\P+q4b35\P+q6b42\[?25l:[?12l[?25h$[?25l[?12l[?25h [?25l14,1All[?12l[?25h[?25l3,0-1[?12l[?25h[?25l-- INSERT --13,1All[?12l[?25h[?25l /usr/local/netfpga/lib/scripts/cpci_reprogram/cpci53[?12l[?25h[?25li_reprogram.pl --all7[?12l[?25h[?25l13,72All[?12l[?25h[?25l3 [?12l[?25h[?25l2[?12l[?25h[?25l1[?12l[?25h[?25l/usr/local/netfpga/lib/scripts/cpci_reprogram/cpci_reprogram.pl --all [?12l[?25h[?25l:[?12l[?25hw[?25l[?12l[?25h [?25l"/etc/rc.local" 14L, 376C written13,1All13,1All[?12l[?25h[?25l[?12l[?25h[?25l2[?12l[?25h[?25l1[?12l[?25h[?25l2[?12l[?25h[?25l3[?12l[?25h[?25l:[?12l[?25hw[?25l[?12l[?25hq[?25l[?12l[?25h [?25l"/etc/rc.local" 14L, 376C written [?1l>[?12l[?25h[?1049l]0;netfpga@node1-1: ~netfpga@node1-1:~$ for i in `seq 0 3`; do ifconfig nf2c$i up; done Command 'ifconfig' is available in '/sbin/ifconfig' The command could not be located because '/sbin' is not included in the PATH environment variable. This is most likely caused by the lack of administrative priviledges associated with your user account. ifconfig: command not found Command 'ifconfig' is available in '/sbin/ifconfig' The command could not be located because '/sbin' is not included in the PATH environment variable. This is most likely caused by the lack of administrative priviledges associated with your user account. ifconfig: command not found Command 'ifconfig' is available in '/sbin/ifconfig' The command could not be located because '/sbin' is not included in the PATH environment variable. This is most likely caused by the lack of administrative priviledges associated with your user account. ifconfig: command not found Command 'ifconfig' is available in '/sbin/ifconfig' The command could not be located because '/sbin' is not included in the PATH environment variable. This is most likely caused by the lack of administrative priviledges associated with your user account. ifconfig: command not found ]0;netfpga@node1-1: ~netfpga@node1-1:~$ sudo vi /etc/rc.local ^[[B vi /etc/rc.local sudos  su - ]0;root@node1-1.sb9.orbit-lab.org: ~root@node1-1:~# exit logout ]0;netfpga@node1-1: ~netfpga@node1-1:~$ sudo bash ]0;root@node1-1: ~root@node1-1:~# for i in `seq 0 3`; do ifconfig nf2c$i up; done ]0;root@node1-1: ~root@node1-1:~# ifconfig control Link encap:Ethernet HWaddr 00:15:17:d6:da:4b inet addr:10.19.1.1 Bcast:10.19.255.255 Mask:255.255.0.0 inet6 addr: fe80::215:17ff:fed6:da4b/64 Scope:Link UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1 RX packets:759 errors:0 dropped:0 overruns:0 frame:0 TX packets:503 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:86985 (86.9 KB) TX bytes:74292 (74.2 KB) Memory:febe0000-fec00000 lo Link encap:Local Loopback inet addr:127.0.0.1 Mask:255.0.0.0 inet6 addr: ::1/128 Scope:Host UP LOOPBACK RUNNING MTU:16436 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:0 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B) nf2c0 Link encap:Ethernet HWaddr 00:4e:46:32:43:00 UP BROADCAST MULTICAST MTU:1500 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B) Interrupt:16 nf2c1 Link encap:Ethernet HWaddr 00:4e:46:32:43:01 UP BROADCAST MULTICAST MTU:1500 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B) Interrupt:16 nf2c2 Link encap:Ethernet HWaddr 00:4e:46:32:43:02 UP BROADCAST MULTICAST MTU:1500 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B) Interrupt:16 nf2c3 Link encap:Ethernet HWaddr 00:4e:46:32:43:03 UP BROADCAST MULTICAST MTU:1500 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B) Interrupt:16 ]0;root@node1-1: ~root@node1-1:~# ls netfpga pkgs ]0;root@node1-1: ~root@node1-1:~# ~ ]0;root@node1-1: ~root@node1-1:~# netfpga/projects/selftest/sw/selftest -n Found net device: nf2c0 Error: Incorrect bitfile loaded. Found 'cpci_reprogrammer' (CPCI Reprogrammer), expecting: 'selftest' ]0;root@node1-1: ~root@node1-1:~# nf_dwoownload netfpga/bnitfiles/selftest.bit Found net device: nf2c0 Bit file built from: nf2_top_par.ncd;HW_TIMEOUT=FALSE Part: 2vp50ff1152 Date: 2011/ 1/20 Time: 14:36:45 Error Registers: 0 Good, after resetting programming interface the FIFO is empty Download completed - 2377668 bytes. (expected 2377668). DONE went high - chip has been successfully programmed. CPCI Information ---------------- Version: 4 (rev 1) Device (Virtex) Information --------------------------- Project directory: selftest Project name: Selftest Project description: NetFPGA selftest -- exercises all major subsystems of the board Device ID: 5 Version: 1.1.0 Built against CPCI version: 4 (rev 1) Virtex design compiled against active CPCI version ]0;root@node1-1: ~root@node1-1:~# ]0;root@node1-1: ~root@node1-1:~# ~/netfpga/projects/selftest/sw/selftest -n  Found net device: nf2c0 CPCI Information ---------------- Version: 4 (rev 1) Device (Virtex) Information --------------------------- Project directory: selftest Project name: Selftest Project description: NetFPGA selftest -- exercises all major subsystems of the board Device ID: 5 Version: 1.1.0 Built against CPCI version: 4 (rev 1) NetFPGA selftest 1.00 alpha Running..... FAILED. Failing tests: PHY interface ]0;root@node1-1: ~root@node1-1:~# less netfpga/projects/selftest/sw/selftest "netfpga/projects/selftest/sw/selftest" may be a binary file. See it anyway? [?1049h[?1h= ^?ELF^A^A^A^@^@^@^@^@^@^@^@^@^B^@^C^@^A^@^@^@@<96>^D^H4^@^@^@l^@^@^@^@^@^@4 ^@ ^@^H^@(^@&^@#^@^F^@^@^@4^@^@^@4<80>^D^H4<80>^D^H^@^A^@^@^@^A^@^@^E^@^@^@^D^@ ^@^@^C^@^@^@4^A^@^@4<81>^D^H4<81>^D^H^S^@^@^@^S^@^@^@^D^@^@^@^A^@^@^@^A^@^@^@^@ ^@^@^@^@<80>^D^H^@<80>^D^H^Pf^@^@^Pf^@^@^E^@^@^@^@^P^@^@^A^@^@^@n^@^@ ^D^H^D^HP^M^@^@^N^@^@^F^@^@^@^@^P^@^@^B^@^@^@n^@^@^D^H^D^H^@^@^@^@^@^@^F^@^@^@^D^@^@^@^D^@^@^@H^A^@^@H<81>^D^HH<81> ^D^HD^@^@^@D^@^@^@^D^@^@^@^D^@^@^@Qtd^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@ ^@^F^@^@^@^D^@^@^@Rtdn^@^@^D^H^D^HL^A^@^@L^A^@^@^D^@^@^@^A^@^@^@/lib/ld-linux.so.2^@^@^D^@^@^@^P^@^@^@^A^@^@^@GNU^@^@^@^@^@^B^@^@^@^F^@ ^@^@^O^@^@^@^D^@^@^@^T^@^@^@^C^@^@^@GNU^@<8B>gW<9B>^HRC2^_R
<86>C^@^@^@^^@^@^@^@^@^@^@^K^@^@^@%^@^@^@^@^@^@^@N^@^@^@^@^@^@^@^@^@ ^@^@6^@^@^@'^@^@^@^@^@^@^@R^@^@^@]^@^@^@^]^@^@^@=^@^@^@@^@^@^@9^@^@^@;^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@-^@^@^@(^@^@^@Z^@^@^@^Q^@^@^@/^@^@^@B^@^@^@K^@^@^@0 ^@^@^@L^@^@^@^M^@^@^@^@^@^@^@^P^@^@^@)^@^@^@1^@^@^@[^@^@^@*^@^@^@^@^@^@^@^S^@^@ ^@8^@^@^@^A^@^@^@2^@^@^@?^@^@^@^X^@^@^@^@^@^@^@"^@^@^@^@^@^@^@4^@^@^@<^@^@^@H^@ ^@^@^E^@^@^@W^@^@^@3^@^@^@Y^@^@^@5^@^@^@^@^@^@^@7^@^@^@^@^@^@^@^@^@^@^@:^@^@^@G ^@^@^@^Z^@^@^@^O^@^@^@^V^@^@^@.^@^@^@J^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^G^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^B^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@ ^@^@^@^H^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@>^@^@^@^F^@^@^@^U^@^@^@O^@^@^@^Y^@^@^@^C^@^@^@^@^@^@^@^@^@^@^@^_^@^@^@!^@^@^@^@^@^@^@C^@^@^@^@^@^@^@A^@^@^@^@^@^@^@E^@^@^@^@^@^@^@ESC^@^@^@#^@^@^@^@^@^@^@T^@^@^@+^@^@^@^R^@^@^@^@^@^@^@^@^@^@^@^^^@^@^@^@^@^@^@^@^@^@^@&^@ ^@^@,^@^@^@I^@^@^@ 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<8B>E <8D>H^E ^L^E^H<8B>UĉT<89>L$^D<89>^D$/<8B>EU<89> <83>(E^T^@^@^@<8B>^G^CE^L<8D>U<89>T<89>D$^D^D$^@^M^E^H5^O^@^@<83>m^A^D$^C^@^@<83>}^@~^G <8B>E<85>xËE<85>y^G^H<8B>E% ^@^@U<89><83>^X<8B>E^P^OЋ^G^CE^L<89>T<89>D$^D^D$: [?1l>[?1049l]0;root@node1-1: ~root@node1-1:~# ls netfpga pkgs ]0;root@node1-1: ~root@node1-1:~# cd netfpga/projects/selftest/sw/ ]0;root@node1-1: ~/netfpga/projects/selftest/swroot@node1-1:~/netfpga/projects/selftest/sw# ls bad_pkt_dump or_utils.o selftest_dram.h selftest_reg.c bad_pkt_dump.c selftest selftest_dram.o selftest_reg.h bad_pkt_dump.o selftest.c selftest.h selftest_reg.o Makefile selftest_clk.c selftest_mdio.c selftest_serial.c or_data_types.h selftest_clk.h selftest_mdio.h selftest_serial.h or_ip.c selftest_clk.o selftest_mdio.o selftest_serial.o or_ip.h selftest_dma.c selftest.o selftest_sram.c or_ip.o selftest_dma.h selftest_phy.c selftest_sram.h or_utils.c selftest_dma.o selftest_phy.h selftest_sram.o or_utils.h selftest_dram.c selftest_phy.o ]0;root@node1-1: ~/netfpga/projects/selftest/swroot@node1-1:~/netfpga/projects/selftest/sw# vi selftest_phy.c [?1049h[?1h=[?12;25h[?12l[?25h[?25l"selftest_phy.c" 157L, 3955C[>c/* **************************************************************************** * vim:set shiftwidth=2 softtabstop=2 expandtab: * $Id: selftest_phy.c 5971 2010-03-06 06:44:56Z grg $ * * Module: selftest_phy.c * Project: NetFPGA selftest * Description: SATA selftest module * * Change history: * */ #include "../lib/C/reg_defines_selftest.h" #include "selftest.h" #include "selftest_phy.h" #include  #include  #define NUM_PORTS 4 static int prev_good_pkts[NUM_PORTS]; static int prev_bad_pkts[NUM_PORTS];1,1Top[?12l[?25hP+q436f\P+q6b75\P+q6b64\P+q6b72\P+q6b6c\P+q2332\P+q2334\P+q2569\P+q2a37\P+q6b31\P+q6b32\[?25l/* **************************************************************************** * vim:set shiftwidth=2 softtabstop=2 expandtab: * $Id: selftest_phy.c 5971 2010-03-06 06:44:56Z grg $ * * Module: selftest_phy.c * Project: NetFPGA selftest * Description: SATA selftest module * * Change history: * */ #include "../lib/C/reg_defines_selftest.h" #include "selftest.h" #include "selftest_phy.h" #include  #include  #define NUM_PORTS 4 static int prev_good_pkts[NUM_PORTS]; static int prev_bad_pkts[NUM_PORTS];1,1Top "selftest_phy.c" 157L, 3955C1,1Top[?12l[?25hP+q6b33\[?25l[?12l[?25hP+q6b34\P+q6b35\P+q6b36\P+q6b37\P+q6b38\P+q6b39\P+q6b3b\P+q4631\P+q4632\P+q2531\P+q2638\P+q6b62\P+q6b49\P+q6b44\P+q6b68\P+q4037\P+q6b50\P+q6b4e\P+q4b31\P+q4b33\P+q4b34\P+q4b35\P+q6b42\[?25l2[?12l[?25h[?25l3[?12l[?25h[?25l4[?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l9[?12l[?25h[?25l10,1[?12l[?25h[?25l1[?12l[?25h[?25l2,0-1[?12l[?25h[?25l3,1 [?12l[?25h[?25l4[?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8,0-1[?12l[?25h[?25l9,1 [?12l[?25h[?25l20,0-1[?12l[?25h[?25l1,1 [?12l[?25h[?25l2[?12l[?25h[?25l3,0-1[?12l[?25h[?25l /*24,10%[?12l[?25h[?25l  * Reset the interface and configure it for continuous operation25,11%[?12l[?25h[?25l  */26,12%[?12l[?25h[?25l void phyResetContinuous(void) {27,12%[?12l[?25h[?25l  int i;28,13%[?12l[?25h[?25l 29,0-14%[?12l[?25h[?25l  for (i = 0; i < NUM_PORTS; i++) {30,15%[?12l[?25h[?25l  prev_good_pkts[i] = 0;31,15%[?12l[?25h[?25l  prev_bad_pkts[i] = 0;32,16%[?12l[?25h[?25l  }33,17%[?12l[?25h[?25l 34,0-18%[?12l[?25h[?25l  // Stop the test (and wait for the test to stop)35,18%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_CTRL_REG, 0x0);36,19%[?12l[?25h[?25l  sleep(1);37,110%[?12l[?25h[?25l 38,0-111%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_PATTERN_REG, PHY_TEST_PATTERN_ENABLE_MASK);39,111%[?12l[?25h[?25l 40,0-112%[?12l[?25h[?25l  // Start the test41,113%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_CTRL_REG, PHY_TEST_CTRL_REPEAT);42,114%[?12l[?25h[?25l {} // phyResetContinuous43,114%[?12l[?25h[?25l {}44,0-115%[?12l[?25h[?25l /*45,116%[?12l[?25h[?25l  * Show the status of the SATA test when running in continuous mode46,117%[?12l[?25h[?25l  *47,117%[?12l[?25h[?25l  * Return -- boolean indicating success48,118%[?12l[?25h[?25l  */49,119%[?12l[?25h[?25l int phyShowStatusContinuous(void) {50,120%[?12l[?25h[?25l  unsigned int val;51,120%[?12l[?25h[?25l  unsigned int port_status;52,121%[?12l[?25h[?25l  unsigned int good_pkts;53,122%[?12l[?25h[?25l  unsigned int bad_pkts;54,123%[?12l[?25h[?25l 55,0-123%[?12l[?25h[?25l  int i;56,124%[?12l[?25h[?25l 57,0-125%[?12l[?25h[?25l  int x, y;58,126%[?12l[?25h[?25l 59,0-126%[?12l[?25h[?25l  int good = 1;60,127%[?12l[?25h[?25l 61,0-128%[?12l[?25h[?25l  // Store the current screen position62,129%[?12l[?25h[?25l  getyx(stdscr, y, x);63,129%[?12l[?25h[?25l 64,0-130%[?12l[?25h[?25l  // Move down a line65,131%[?12l[?25h[?25l  move(y + 1, x);66,132%[?12l[?25h[?25l 67,0-132%[?12l[?25h[?25l  // Read the individual port registers68,133%[?12l[?25h[?25l  for (i = 0; i < NUM_PORTS; i++) {69,134%[?12l[?25h[?25l  printw(" Port %d:", i + 1);70,135%[?12l[?25h[?25l 71,0-135%[?12l[?25h[?25l  // Start with the status register72,136%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_STATUS_REG + i * PHY_TEST_PHY_GROUP_INST_OFFFSET, &port_status);73,137%[?12l[?25h[?25l  if (port_status & 0x100) {74,138%[?12l[?25h[?25l  printw(" link w/ %d", (port_status & 0xf0000) >> 16);75,139%[?12l[?25h[?25l  }76,140%[?12l[?25h[?25l  else {77,140%[?12l[?25h[?25l  printw(" no link");78,141%[?12l[?25h[?25l  good = 0;79,142%[?12l[?25h[?25l  }80,142%[?12l[?25h[?25l 81,0-143%[?12l[?25h[?25l  // Read the number of good/bad packets82,144%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_GOOD_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INNST_OFFSET, &good_pkts);83,145%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_ERR_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INNST_OFFSET, &bad_pkts);84,146%[?12l[?25h[?25l  printw(" Good: %d Bad: %d", good_pkts, bad_pkts);85,147%[?12l[?25h[?25l 86,0-148%[?12l[?25h[?25l  printw("\n");87,148%[?12l[?25h[?25l 88,0-149%[?12l[?25h[?25l  // Verify if we should reset the counters89,150%[?12l[?25h[?25l  /*if ((port_status & 0x1100) == 0x1100) {90,151%[?12l[?25h[?25l  // Only reset if the number of good packets has incremented but the bad91,151%[?12l[?25h[?25l  // packets have remained the same92,152%[?12l[?25h[?25l if (bad_pkts == prev_bad_pkts[i] && good_pkts != prev_good_pkts[i]) { writeReg(&nf2, PHY_TEST_PHY_0_RX_CTRL_REG + i * PHY_TEST_PHY_GROUP_INST_@ 93,153%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_PHY_0_RX_CTRL_REG + i * PHY_TEST_PHY_GROUP_INST__OFFSET, 0x3);94,154%[?12l[?25h[?25l  }95,154%[?12l[?25h[?25l 96,0-155%[?12l[?25h[?25l  // Update the counters97,156%[?12l[?25h[?25l  prev_bad_pkts[i] = bad_pkts;98,156%[?12l[?25h[?25l  prev_good_pkts[i] = good_pkts;99,157%[?12l[?25h[?25l  }*/100,158%[?12l[?25h[?25l 101,0-159%[?12l[?25h[?25l  // Update the good flag102,159%[?12l[?25h[?25l if (bad_pkts != 0) good = 0;103,161%[?12l[?25h[?25l4[?12l[?25h[?25l }105,162%[?12l[?25h[?25l6,0-1[?12l[?25h[?25l  // Print overall success/failure107,162%[?12l[?25h[?25l  move(y, x);108,163%[?12l[?25h[?25l  printw("PHY test: %s", good ? "pass" : "fail");109,164%[?12l[?25h[?25l  move(y + 1 + NUM_PORTS, x);110,165%[?12l[?25h[?25l 111,0-165%[?12l[?25h[?25l  return good;112,166%[?12l[?25h[?25l } // phyShowStatusContinuous113,167%[?12l[?25h[?25l 114,0-168%[?12l[?25h[?25l /*115,168%[?12l[?25h[?25l * Stop the interface */116,170%[?12l[?25h[?25l7[?12l[?25h[?25l void phyStopContinuous(void) {118,170%[?12l[?25h[?25l  // Stop the test (and wait for the test to stop)119,171%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_CTRL_REG, 0x00000000);120,172%[?12l[?25h[?25l { } // phyStopContinuous121,173%[?12l[?25h[?25l { }122,0-173%[?12l[?25h[?25l /*123,174%[?12l[?25h[?25l  * Get the result of the test124,175%[?12l[?25h[?25l  *125,176%[?12l[?25h[?25l  * Return -- boolean indicating success126,176%[?12l[?25h[?25l  */127,177%[?12l[?25h[?25l int phyGetResult(void) {128,178%[?12l[?25h[?25l  unsigned int val;129,179%[?12l[?25h[?25l  unsigned int port_status;130,179%[?12l[?25h[?25l  unsigned int good_pkts;131,180%[?12l[?25h[?25l  unsigned int bad_pkts;132,181%[?12l[?25h[?25l 133,0-182%[?12l[?25h[?25l  int i;134,182%[?12l[?25h[?25l 135,0-183%[?12l[?25h[?25l  int good = 1;136,184%[?12l[?25h[?25l 137,0-185%[?12l[?25h[?25l  // Read the individual port registers138,185%[?12l[?25h[?25l  for (i = 0; i < NUM_PORTS; i++) {139,186%[?12l[?25h[?25l  // Start with the status register140,187%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_STATUS_REG + i * PHY_TEST_PHY_GROUP_INST_OFFFSET, &port_status);141,188%[?12l[?25h[?25l  if ((port_status & 0x100) == 0) {142,188%[?12l[?25h[?25l  good = 0;143,189%[?12l[?25h[?25l  }144,190%[?12l[?25h[?25l 145,0-191%[?12l[?25h[?25l  // Read the number of good/bad packets146,191%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_GOOD_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INNST_OFFSET, &good_pkts);147,192%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_ERR_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INSST_OFFSET, &bad_pkts);148,193%[?12l[?25h[?25l 149,0-194%[?12l[?25h[?25l  // Update the good flag150,194%[?12l[?25h[?25l  if (bad_pkts != 0) {151,195%[?12l[?25h[?25l  good = 0;152,196%[?12l[?25h[?25l  }153,197%[?12l[?25h[?25l  }154,197%[?12l[?25h[?25l 155,0-198%[?12l[?25h[?25l  return good;156,199%[?12l[?25h[?25l } // phyGetResult157,1Bot[?12l[?25h[?25l6[?12l[?25h[?25l5,0-1[?12l[?25h[?25l4,1 [?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l1[?12l[?25h[?25l0[?12l[?25h[?25l49,0-1[?12l[?25h[?25l8,1 [?12l[?25h[?25l7[?12l[?25h[?25l6[?12l[?25h[?25l5,0-1[?12l[?25h[?25l4,1 [?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l1[?12l[?25h[?25l0[?12l[?25h[?25l39[?12l[?25h[?25l8[?12l[?25h[?25l137,0-199%[?12l[?25h[?25l int good = 1;136,198%[?12l[?25h[?25l135,0-197%[?12l[?25h[?25l int i;134,197%[?12l[?25h[?25l133,0-196%[?12l[?25h[?25l unsigned int bad_pkts;132,195%[?12l[?25h[?25l unsigned int good_pkts;131,194%[?12l[?25h[?25l unsigned int port_status;130,194%[?12l[?25h[?25l unsigned int val;129,193%[?12l[?25h[?25lint phyGetResult(void) {@ 128,192%[?12l[?25h[?25l */127,192%[?12l[?25h[?25l * Return -- boolean indicating success@ 126,191%[?12l[?25h[?25l *125,191%[?12l[?25h[?25l * Get the result of the test124,191%[?12l[?25h[?25l/*123,190%[?12l[?25h[?25l122,0-189%[?12l[?25h[?25l} // phyStopContinuous121,188%[?12l[?25h[?25l writeReg(&nf2, PHY_TEST_CTRL_REG, 0x00000000);120,188%[?12l[?25h[?25l // Stop the test (and wait for the test to stop)@ 119,187%[?12l[?25h[?25lvoid phyStopContinuous(void) {118,187%[?12l[?25h[?25l */117,186%[?12l[?25h[?25l * Stop the interface116,185%[?12l[?25h[?25l/*115,185%[?12l[?25h[?25l114,0-184%[?12l[?25h[?25l} // phyShowStatusContinuous113,183%[?12l[?25h[?25l return good;112,182%[?12l[?25h[?25l111,0-182%[?12l[?25h[?25l move(y + 1 + NUM_PORTS, x);110,181%[?12l[?25h[?25l printw("PHY test: %s", good ? "pass" : "fail");109,180%[?12l[?25h[?25l move(y, x);108,179%[?12l[?25h[?25l // Print overall success/failure107,179%[?12l[?25h[?25l106,0-178%[?12l[?25h[?25l }105,177%[?12l[?25h[?25l good = 0;104,176%[?12l[?25h[?25l if (bad_pkts != 0)103,176%[?12l[?25h[?25l // Update the good flag102,175%[?12l[?25h[?25l101,0-174%[?12l[?25h[?25l }*/100,173%[?12l[?25h[?25l prev_good_pkts[i] = good_pkts;99,173%[?12l[?25h[?25l prev_bad_pkts[i] = bad_pkts;98,172%[?12l[?25h[?25l // Update the counters97,171%[?12l[?25h[?25l8[?12l[?25h[?25l7[?12l[?25h[?25l96,0-170%[?12l[?25h[?25l }95,170%[?12l[?25h[?25l writeReg(&nf2, PHY_TEST_PHY_0_RX_CTRL_REG + i * PHY_TEST_PHY_GROUP_INST__OFFSET, 0x3);94,168%[?12l[?25h[?25l if (bad_pkts == prev_bad_pkts[i] && good_pkts != prev_good_pkts[i]) {93,168%[?12l[?25h[?25l // packets have remained the same92,167%[?12l[?25h[?25l // Only reset if the number of good packets has incremented but the bad91,166%[?12l[?25h[?25l /*if ((port_status & 0x1100) == 0x1100) {90,165%[?12l[?25h[?25l:[?12l[?25hq[?25l[?12l[?25h [?25l[?1l>[?12l[?25h[?1049l]0;root@node1-1: ~/netfpga/projects/selftest/swroot@node1-1:~/netfpga/projects/selftest/sw# ls bad_pkt_dump or_utils.o selftest_dram.h selftest_reg.c bad_pkt_dump.c selftest selftest_dram.o selftest_reg.h bad_pkt_dump.o selftest.c selftest.h selftest_reg.o Makefile selftest_clk.c selftest_mdio.c selftest_serial.c or_data_types.h selftest_clk.h selftest_mdio.h selftest_serial.h or_ip.c selftest_clk.o selftest_mdio.o selftest_serial.o or_ip.h selftest_dma.c selftest.o selftest_sram.c or_ip.o selftest_dma.h selftest_phy.c selftest_sram.h or_utils.c selftest_dma.o selftest_phy.h selftest_sram.o or_utils.h selftest_dram.c selftest_phy.o ]0;root@node1-1: ~/netfpga/projects/selftest/swroot@node1-1:~/netfpga/projects/selftest/sw# grep PHY | more* | mreoore bad_pkt_dump.c: readReg(&nf2, PHY_TEST_PHY_0_RX_LOG_STATUS_REG, &val); bad_pkt_dump.c: readReg(&nf2, PHY_TEST_PHY_0_RX_LOG_EXP_DATA_REG, &val); bad_pkt_dump.c: readReg(&nf2, PHY_TEST_PHY_0_RX_LOG_RX_DATA_REG, &val); bad_pkt_dump.c: writeReg(&nf2, PHY_TEST_PHY_0_RX_LOG_CTRL_REG, 1); Binary file selftest matches selftest.c: "PHY interface", selftest_mdio.c: for (phy = 0; phy < MAX_PHY_PORTS; phy++) { selftest_mdio.c: // Read the PHY ID register selftest_mdio.c: phyid_hi = readMDIOReg(phy, MDIO_PHY_0_PHY_ID_HI_REG); selftest_mdio.c: phyid_lo = readMDIOReg(phy, MDIO_PHY_0_PHY_ID_LO_REG); selftest_mdio.c: auxstatus = readMDIOReg(phy, MDIO_PHY_0_AUX_STATUS_REG); selftest_mdio.c: printw(" Invalid PHY Id (Read failed)"); selftest_mdio.c: else if ((phyid & 0xfffffff0) != 0x002060B0) { //Invalid PHY Id: 0x007f60b1 up, 1000Base-TX full selftest_mdio.c: printw(" Invalid PHY Id: 0x%08x", phyid); selftest_mdio.c: move(y + 1 + MAX_PHY_PORTS, x); selftest_mdio.c: readReg(&nf2, phy * MDIO_PHY_GROUP_INST_OFFSET + addr, &val) ; selftest_mdio.c: writeReg(&nf2, phy * MDIO_PHY_GROUP_INST_OFFSET + addr, val & 0xffff); selftest_mdio.c: for (phy = 0; phy < MAX_PHY_PORTS; phy++) { selftest_mdio.c: // Read the PHY ID register selftest_mdio.c: phyid_hi = readMDIOReg(phy, MDIO_PHY_0_PHY_ID_HI_REG); --More-- ]0;root@node1-1: ~/netfpga/projects/selftest/swroot@node1-1:~/netfpga/projects/selftest/sw# vi selftest.c [?1049h[?1h=[?12;25h[?12l[?25h[?25l"selftest.c" 512L, 10370C[>c/* **************************************************************************** * vim:set shiftwidth=2 softtabstop=2 expandtab: * $Id: selftest.c 6010 2010-03-14 08:24:50Z grg $ * * Module: selftest.c * Project: NetFPGA 2.1 * Description: Interface with the self-test modules on the NetFPGA * to help diagnose problems. * * Change history: * */ #include  #include  #include  #include  #include  #include  #include  #include 1,1Top[?12l[?25hP+q436f\P+q6b75\P+q6b64\P+q6b72\P+q6b6c\P+q2332\P+q2334\P+q2569\P+q2a37\P+q6b31\P+q6b32\[?25l/* **************************************************************************** * vim:set shiftwidth=2 softtabstop=2 expandtab: * $Id: selftest.c 6010 2010-03-14 08:24:50Z grg $ * * Module: selftest.c * Project: NetFPGA 2.1 * Description: Interface with the self-test modules on the NetFPGA * to help diagnose problems. * * Change history: * */ #include  #include  #include  #include  #include  #include  #include  #include 1,1Top "selftest.c" 512L, 10370C1,1Top[?12l[?25hP+q6b33\[?25l[?12l[?25hP+q6b34\P+q6b35\P+q6b36\P+q6b37\P+q6b38\P+q6b39\P+q6b3b\P+q4631\P+q4632\P+q2531\P+q2638\P+q6b62\P+q6b49\P+q6b44\P+q6b68\P+q4037\P+q6b50\P+q6b4e\P+q4b31\P+q4b33\P+q4b34\P+q4b35\P+q6b42\[?25l/[?12l[?25hP[?25l[?12l[?25hH[?25l[?12l[?25hY[?25l[?12l[?25h [?25l regStopContinuous, regGetResult, }, { "MDIO interface", mdioResetContinuous, mdioShowStatusContinuous, mdioStopContinuous, mdioGetResult, }, { "PHY interface", phyResetContinuous, phyShowStatusContinuous, phyStopContinuous, phyGetResult, }, { "DRAM controller", dramResetContinuous, dramShowStatusContinuous, dramStopContinuous, dramGetResult,110,620%[?12l[?25h[?25l/PHYsearch hit BOTTOM, continuing at TOP110,620%110,620%[?12l[?25h[?25l1[?12l[?25h[?25l2[?12l[?25h[?25l3[?12l[?25h[?25l4[?12l[?25h[?25l5,4[?12l[?25h[?25l6,3[?12l[?25h[?25l7,6[?12l[?25h[?25l8[?12l[?25h[?25l9[?12l[?25h[?25l20[?12l[?25h[?25l1[?12l[?25h[?25l  },122,420%[?12l[?25h[?25l  {123,320%[?12l[?25h[?25l  "SRAM controller",124,620%[?12l[?25h[?25l  sramResetContinuous,125,620%[?12l[?25h[?25l  sramShowStatusContinuous,126,621%[?12l[?25h[?25l  sramStopContinuous,127,621%[?12l[?25h[?25l  sramGetResult,128,621%[?12l[?25h[?25l  },129,421%[?12l[?25h[?25l  {130,321%[?12l[?25h[?25l  "SATA controller",131,622%[?12l[?25h[?25l  serialResetContinuous,132,622%[?12l[?25h[?25l  serialShowStatusContinuous,133,622%[?12l[?25h[?25l  serialStopContinuous,134,622%[?12l[?25h[?25l  serialGetResult,135,622%[?12l[?25h[?25l  },136,423%[?12l[?25h[?25l  {137,323%[?12l[?25h[?25l  "DMA interface",138,623%[?12l[?25h[?25l  dmaResetContinuous,139,623%[?12l[?25h[?25l  dmaShowStatusContinuous,140,623%[?12l[?25h[?25l  dmaStopContinuous,141,624%[?12l[?25h[?25l  dmaGetResult,142,624%[?12l[?25h[?25l  },143,424%[?12l[?25h[?25l };144,224%[?12l[?25h[?25l 145,0-124%[?12l[?25h[?25l 146,0-125%[?12l[?25h[?25l /*147,225%[?12l[?25h[?25l  * Main function148,625%[?12l[?25h[?25l  */149,325%[?12l[?25h[?25l int main(int argc, char *argv[])150,625%[?12l[?25h[?25l {151,126%[?12l[?25h[?25l  // Set the default device152,626%[?12l[?25h[?25l  nf2.device_name = DEFAULT_IFACE;153,626%[?12l[?25h[?25l 154,0-126%[?12l[?25h[?25l  // Process the command line arguments155,626%[?12l[?25h[?25l  processArgs(argc, argv);156,627%[?12l[?25h[?25l 157,0-127%[?12l[?25h[?25l  // Check that the interface is valid and open it if possible158,627%[?12l[?25h[?25l  if (check_iface(&nf2))159,627%[?12l[?25h[?25l () {160,328%[?12l[?25h[?25l  exit(1);161,628%[?12l[?25h[?25l { }162,328%[?12l[?25h[?25l { } if (openDescriptor(&nf2))163,628%[?12l[?25h[?25l () {164,328%[?12l[?25h[?25l  exit(1);165,629%[?12l[?25h[?25l { }166,329%[?12l[?25h[?25l { }167,0-129%[?12l[?25h[?25l  // Verify that the correct device is downloaded168,629%[?12l[?25h[?25l  if (!checkVirtexBitfile(&nf2, DEVICE_PROJ_DIR,169,629%[?12l[?25h[?25l  DEVICE_MAJOR, DEVICE_MINOR, VERSION_ANY,170,1-830%[?12l[?25h[?25l  DEVICE_MAJOR, DEVICE_MINOR, VERSION_ANY)) {171,1-830%[?12l[?25h[?25l  fprintf(stderr, "%s\n", getVirtexBitfileErr());172,630%[?12l[?25h[?25l  exit(1);173,630%[?12l[?25h[?25l { }174,330%[?12l[?25h[?25l {} else {175,631%[?12l[?25h[?25l  printf(getDeviceInfoStr(&nf2));176,631%[?12l[?25h[?25l { }177,331%[?12l[?25h[?25l { }178,0-131%[?12l[?25h[?25l  // Add a signal handler179,631%[?12l[?25h[?25l  signal(SIGINT, sigint_handler);180,632%[?12l[?25h[?25l 181,0-132%[?12l[?25h[?25l  // Measure the clock rates182,632%[?12l[?25h[?25l  measureClocks();183,632%[?12l[?25h[?25l 184,0-132%[?12l[?25h[?25l  // Run the appropriate test185,633%[?12l[?25h[?25l  if (continuous) {186,633%[?12l[?25h[?25l () mainContinuous();187,633%[?12l[?25h[?25l { }188,333%[?12l[?25h[?25l { } else if (shortrun) {189,633%[?12l[?25h[?25l  mainOneShot();190,634%[?12l[?25h[?25l { }191,334%[?12l[?25h[?25l { }192,0-134%[?12l[?25h[?25l  // Close the network descriptor193,634%[?12l[?25h[?25l  closeDescriptor(&nf2);194,634%[?12l[?25h[?25l 195,0-135%[?12l[?25h[?25l  return 0;196,635%[?12l[?25h[?25l }197,135%[?12l[?25h[?25l 198,0-135%[?12l[?25h[?25l /*199,235%[?12l[?25h[?25l  * "Main" function for continuous mode200,636%[?12l[?25h[?25l  */201,336%[?12l[?25h[?25l void mainContinuous(void)202,636%[?12l[?25h[?25l {203,136%[?12l[?25h[?25l  // Set up curses204,637%[?12l[?25h[?25l  w = initscr();205,637%[?12l[?25h[?25l  cbreak();206,637%[?12l[?25h[?25l:[?12l[?25h1[?25l[?12l[?25h [?25l/* **************************************************************************** * vim:set shiftwidth=2 softtabstop=2 expandtab: * $Id: selftest.c 6010 2010-03-14 08:24:50Z grg $ * * Module: selftest.c * Project: NetFPGA 2.1 * Description: Interface with the self-test modules on the NetFPGA * to help diagnose problems. * * Change history: * */ #include  #include  #include  #include  #include  #include  #include  #include 1,1Top[?12l[?25h[?25l/PHY regStopContinuous, regGetResult, }, { "MDIO interface", mdioResetContinuous, mdioShowStatusContinuous, mdioStopContinuous, mdioGetResult, }, { "PHY interface", phyResetContinuous, phyShowStatusContinuous, phyStopContinuous, phyGetResult, }, { "DRAM controller", dramResetContinuous, dramShowStatusContinuous, dramStopContinuous, dramGetResult,110,620%[?12l[?25h[?25l1[?12l[?25h[?25l:[?12l[?25hq[?25l[?12l[?25h [?25l[?1l>[?12l[?25h[?1049l]0;root@node1-1: ~/netfpga/projects/selftest/swroot@node1-1:~/netfpga/projects/selftest/sw# vi selftest.cgrep PHY * | morelsvi selftest_phy.c [?1049h[?1h=[?12;25h[?12l[?25h[?25l"selftest_phy.c" 157L, 3955C[>c/* **************************************************************************** * vim:set shiftwidth=2 softtabstop=2 expandtab: * $Id: selftest_phy.c 5971 2010-03-06 06:44:56Z grg $ * * Module: selftest_phy.c * Project: NetFPGA selftest * Description: SATA selftest module * * Change history: * */ #include "../lib/C/reg_defines_selftest.h" #include "selftest.h" #include "selftest_phy.h" #include  #include  #define NUM_PORTS 4 static int prev_good_pkts[NUM_PORTS]; static int prev_bad_pkts[NUM_PORTS];1,1Top[?12l[?25hP+q436f\P+q6b75\P+q6b64\P+q6b72\P+q6b6c\P+q2332\P+q2334\P+q2569\P+q2a37\P+q6b31\P+q6b32\[?25l/* **************************************************************************** * vim:set shiftwidth=2 softtabstop=2 expandtab: * $Id: selftest_phy.c 5971 2010-03-06 06:44:56Z grg $ * * Module: selftest_phy.c * Project: NetFPGA selftest * Description: SATA selftest module * * Change history: * */ #include "../lib/C/reg_defines_selftest.h" #include "selftest.h" #include "selftest_phy.h" #include  #include  #define NUM_PORTS 4 static int prev_good_pkts[NUM_PORTS]; static int prev_bad_pkts[NUM_PORTS];1,1Top "selftest_phy.c" 157L, 3955C1,1Top[?12l[?25hP+q6b33\[?25l[?12l[?25hP+q6b34\P+q6b35\P+q6b36\P+q6b37\P+q6b38\P+q6b39\P+q6b3b\P+q4631\P+q4632\P+q2531\P+q2638\P+q6b62\P+q6b49\P+q6b44\P+q6b68\P+q4037\P+q6b50\P+q6b4e\P+q4b31\P+q4b33\P+q4b34\P+q4b35\P+q6b42\[?25lstatic int prev_bad_pkts[NUM_PORTS]; /* * Reset the interface and configure it for continuous operation */ void phyResetContinuous(void) { int i; for (i = 0; i < NUM_PORTS; i++) { prev_good_pkts[i] = 0; prev_bad_pkts[i] = 0; } // Stop the test (and wait for the test to stop) writeReg(&nf2, PHY_TEST_CTRL_REG, 0x0); sleep(1); writeReg(&nf2, PHY_TEST_PATTERN_REG, PHY_TEST_PATTERN_ENABLE_MASK); // Start the test writeReg(&nf2, PHY_TEST_CTRL_REG, PHY_TEST_CTRL_REPEAT); } // phyResetContinuous22,115%[?12l[?25h[?25l3,0-1[?12l[?25h[?25l4,1 [?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l9,0-1[?12l[?25h[?25l30,1 [?12l[?25h[?25l1[?12l[?25h[?25l2[?12l[?25h[?25l3[?12l[?25h[?25l4,0-1[?12l[?25h[?25l5,1 [?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8,0-1[?12l[?25h[?25l9,1 [?12l[?25h[?25l40,0-1[?12l[?25h[?25l1,1 [?12l[?25h[?25l2[?12l[?25h[?25l{}3[?12l[?25h[?25l{}4,0-1[?12l[?25h[?25l /*45,116%[?12l[?25h[?25l  * Show the status of the SATA test when running in continuous mode46,117%[?12l[?25h[?25l  *47,117%[?12l[?25h[?25l  * Return -- boolean indicating success48,118%[?12l[?25h[?25l  */49,119%[?12l[?25h[?25l int phyShowStatusContinuous(void) {50,120%[?12l[?25h[?25l  unsigned int val;51,120%[?12l[?25h[?25l  unsigned int port_status;52,121%[?12l[?25h[?25l  unsigned int good_pkts;53,122%[?12l[?25h[?25l  unsigned int bad_pkts;54,123%[?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l1[?12l[?25h[?25l0[?12l[?25h[?25l49[?12l[?25h[?25l8[?12l[?25h[?25l7[?12l[?25h[?25l6[?12l[?25h[?25l5[?12l[?25h[?25l4,0-1[?12l[?25h[?25l3,1 [?12l[?25h[?25l2[?12l[?25h[?25l1[?12l[?25h[?25l0,0-1[?12l[?25h[?25l39,1 [?12l[?25h[?25l8,0-1[?12l[?25h[?25l7,1 [?12l[?25h[?25l6[?12l[?25h[?25l5[?12l[?25h[?25l4,0-1[?12l[?25h[?25l3,1 [?12l[?25h[?25l2[?12l[?25h[?25l prev_good_pkts[i] = 0;31,122%[?12l[?25h[?25l for (i = 0; i < NUM_PORTS; i++) {30,121%[?12l[?25h[?25l29,0-120%[?12l[?25h[?25l int i;28,120%[?12l[?25h[?25lvoid phyResetContinuous(void) {27,119%[?12l[?25h[?25l */26,118%[?12l[?25h[?25l * Reset the interface and configure it for continuous operation25,117%[?12l[?25h[?25l/*24,117%[?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l9,0-1[?12l[?25h[?25l30,1 [?12l[?25h[?25l1[?12l[?25h[?25l2[?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l1[?12l[?25h[?25l0[?12l[?25h[?25l29,0-1[?12l[?25h[?25l8,1 [?12l[?25h[?25l7[?12l[?25h[?25l6[?12l[?25h[?25l5[?12l[?25h[?25l4[?12l[?25h[?25l23,0-116%[?12l[?25h[?25lstatic int prev_bad_pkts[NUM_PORTS];22,115%[?12l[?25h[?25lstatic int prev_good_pkts[NUM_PORTS];21,114%[?12l[?25h[?25l20,0-114%[?12l[?25h[?25l#define NUM_PORTS 419,113%[?12l[?25h[?25l18,0-112%[?12l[?25h[?25l#include 17,111%[?12l[?25h[?25l#include 16,111%[?12l[?25h[?25l#include "selftest_phy.h"15,110%[?12l[?25h[?25l#include "selftest.h"14,19%[?12l[?25h[?25l#include "../lib/C/reg_defines_selftest.h"13,18%[?12l[?25h[?25l12,0-18%[?12l[?25h[?25l */11,17%[?12l[?25h[?25l2,0-1[?12l[?25h[?25l3,1 [?12l[?25h[?25l4[?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8,0-1[?12l[?25h[?25l9,1 [?12l[?25h[?25l20,0-1[?12l[?25h[?25l1,1 [?12l[?25h[?25l2[?12l[?25h[?25l3,0-1[?12l[?25h[?25l4,1 [?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l9,0-1[?12l[?25h[?25l30,1 [?12l[?25h[?25l1[?12l[?25h[?25l2[?12l[?25h[?25l3[?12l[?25h[?25l 34,0-18%[?12l[?25h[?25l  // Stop the test (and wait for the test to stop)35,18%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_CTRL_REG, 0x0);36,19%[?12l[?25h[?25l  sleep(1);37,110%[?12l[?25h[?25l 38,0-111%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_PATTERN_REG, PHY_TEST_PATTERN_ENABLE_MASK);39,111%[?12l[?25h[?25l 40,0-112%[?12l[?25h[?25l  // Start the test41,113%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_CTRL_REG, PHY_TEST_CTRL_REPEAT);42,114%[?12l[?25h[?25l {} // phyResetContinuous43,114%[?12l[?25h[?25l {}44,0-115%[?12l[?25h[?25l /*45,116%[?12l[?25h[?25l  * Show the status of the SATA test when running in continuous mode46,117%[?12l[?25h[?25l  *47,117%[?12l[?25h[?25l  * Return -- boolean indicating success48,118%[?12l[?25h[?25l  */49,119%[?12l[?25h[?25l int phyShowStatusContinuous(void) {50,120%[?12l[?25h[?25l  unsigned int val;51,120%[?12l[?25h[?25l  unsigned int port_status;52,121%[?12l[?25h[?25l  unsigned int good_pkts;53,122%[?12l[?25h[?25l  unsigned int bad_pkts;54,123%[?12l[?25h[?25l 55,0-123%[?12l[?25h[?25l  int i;56,124%[?12l[?25h[?25l 57,0-125%[?12l[?25h[?25l  int x, y;58,126%[?12l[?25h[?25l 59,0-126%[?12l[?25h[?25l  int good = 1;60,127%[?12l[?25h[?25l 61,0-128%[?12l[?25h[?25l  // Store the current screen position62,129%[?12l[?25h[?25l  getyx(stdscr, y, x);63,129%[?12l[?25h[?25l 64,0-130%[?12l[?25h[?25l  // Move down a line65,131%[?12l[?25h[?25l  move(y + 1, x);66,132%[?12l[?25h[?25l 67,0-132%[?12l[?25h[?25l  // Read the individual port registers68,133%[?12l[?25h[?25l  for (i = 0; i < NUM_PORTS; i++) {69,134%[?12l[?25h[?25l  printw(" Port %d:", i + 1);70,135%[?12l[?25h[?25l 71,0-135%[?12l[?25h[?25l  // Start with the status register72,136%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_STATUS_REG + i * PHY_TEST_PHY_GROUP_INST_OFFFSET, &port_status);73,137%[?12l[?25h[?25l  if (port_status & 0x100) {74,138%[?12l[?25h[?25l  printw(" link w/ %d", (port_status & 0xf0000) >> 16);75,139%[?12l[?25h[?25l  }76,140%[?12l[?25h[?25l  else {77,140%[?12l[?25h[?25l  printw(" no link");78,141%[?12l[?25h[?25l  good = 0;79,142%[?12l[?25h[?25l  }80,142%[?12l[?25h[?25l 81,0-143%[?12l[?25h[?25l  // Read the number of good/bad packets82,144%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_GOOD_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INNST_OFFSET, &good_pkts);83,145%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_ERR_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INNST_OFFSET, &bad_pkts);84,146%[?12l[?25h[?25l  printw(" Good: %d Bad: %d", good_pkts, bad_pkts);85,147%[?12l[?25h[?25l 86,0-148%[?12l[?25h[?25l  printw("\n");87,148%[?12l[?25h[?25l 88,0-149%[?12l[?25h[?25l  // Verify if we should reset the counters89,150%[?12l[?25h[?25l  /*if ((port_status & 0x1100) == 0x1100) {90,151%[?12l[?25h[?25l  // Only reset if the number of good packets has incremented but the bad91,151%[?12l[?25h[?25l  // packets have remained the same92,152%[?12l[?25h[?25l if (bad_pkts == prev_bad_pkts[i] && good_pkts != prev_good_pkts[i]) { writeReg(&nf2, PHY_TEST_PHY_0_RX_CTRL_REG + i * PHY_TEST_PHY_GROUP_INST_@ 93,153%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_PHY_0_RX_CTRL_REG + i * PHY_TEST_PHY_GROUP_INST__OFFSET, 0x3);94,154%[?12l[?25h[?25l  }95,154%[?12l[?25h[?25l 96,0-155%[?12l[?25h[?25l  // Update the counters97,156%[?12l[?25h[?25l  prev_bad_pkts[i] = bad_pkts;98,156%[?12l[?25h[?25l  prev_good_pkts[i] = good_pkts;99,157%[?12l[?25h[?25l  }*/100,158%[?12l[?25h[?25l 101,0-159%[?12l[?25h[?25l  // Update the good flag102,159%[?12l[?25h[?25l if (bad_pkts != 0) good = 0;103,161%[?12l[?25h[?25l4[?12l[?25h[?25l }105,162%[?12l[?25h[?25l6,0-1[?12l[?25h[?25l  // Print overall success/failure107,162%[?12l[?25h[?25l  move(y, x);108,163%[?12l[?25h[?25l  printw("PHY test: %s", good ? "pass" : "fail");109,164%[?12l[?25h[?25l  move(y + 1 + NUM_PORTS, x);110,165%[?12l[?25h[?25l 111,0-165%[?12l[?25h[?25l  return good;112,166%[?12l[?25h[?25l } // phyShowStatusContinuous113,167%[?12l[?25h[?25l 114,0-168%[?12l[?25h[?25l /*115,168%[?12l[?25h[?25l * Stop the interface */116,170%[?12l[?25h[?25l7[?12l[?25h[?25l void phyStopContinuous(void) {118,170%[?12l[?25h[?25l  // Stop the test (and wait for the test to stop)119,171%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_CTRL_REG, 0x00000000);120,172%[?12l[?25h[?25l { } // phyStopContinuous121,173%[?12l[?25h[?25l { }122,0-173%[?12l[?25h[?25l /*123,174%[?12l[?25h[?25l  * Get the result of the test124,175%[?12l[?25h[?25l  *125,176%[?12l[?25h[?25l  * Return -- boolean indicating success126,176%[?12l[?25h[?25l  */127,177%[?12l[?25h[?25l int phyGetResult(void) {128,178%[?12l[?25h[?25l  unsigned int val;129,179%[?12l[?25h[?25l  unsigned int port_status;130,179%[?12l[?25h[?25l  unsigned int good_pkts;131,180%[?12l[?25h[?25l  unsigned int bad_pkts;132,181%[?12l[?25h[?25l 133,0-182%[?12l[?25h[?25l  int i;134,182%[?12l[?25h[?25l 135,0-183%[?12l[?25h[?25l  int good = 1;136,184%[?12l[?25h[?25l 137,0-185%[?12l[?25h[?25l  // Read the individual port registers138,185%[?12l[?25h[?25l  for (i = 0; i < NUM_PORTS; i++) {139,186%[?12l[?25h[?25l  // Start with the status register140,187%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_STATUS_REG + i * PHY_TEST_PHY_GROUP_INST_OFFFSET, &port_status);141,188%[?12l[?25h[?25l  if ((port_status & 0x100) == 0) {142,188%[?12l[?25h[?25l  good = 0;143,189%[?12l[?25h[?25l  }144,190%[?12l[?25h[?25l 145,0-191%[?12l[?25h[?25l  // Read the number of good/bad packets146,191%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_GOOD_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INNST_OFFSET, &good_pkts);147,192%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_ERR_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INSST_OFFSET, &bad_pkts);148,193%[?12l[?25h[?25l 149,0-194%[?12l[?25h[?25l  // Update the good flag150,194%[?12l[?25h[?25l  if (bad_pkts != 0) {151,195%[?12l[?25h[?25l  good = 0;152,196%[?12l[?25h[?25l  }153,197%[?12l[?25h[?25l  }154,197%[?12l[?25h[?25l 155,0-198%[?12l[?25h[?25l  return good;156,199%[?12l[?25h[?25l } // phyGetResult157,1Bot[?12l[?25h[?25l6[?12l[?25h[?25l5,0-1[?12l[?25h[?25l4,1 [?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l1[?12l[?25h[?25l0[?12l[?25h[?25l49,0-1[?12l[?25h[?25l8,1 [?12l[?25h[?25l7[?12l[?25h[?25l6[?12l[?25h[?25l5,0-1[?12l[?25h[?25l4,1 [?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l1[?12l[?25h[?25l0[?12l[?25h[?25l39[?12l[?25h[?25l8[?12l[?25h[?25l137,0-199%[?12l[?25h[?25l int good = 1;136,198%[?12l[?25h[?25l135,0-197%[?12l[?25h[?25l int i;134,197%[?12l[?25h[?25l133,0-196%[?12l[?25h[?25l:[?12l[?25h1[?25l[?12l[?25h [?25l/* **************************************************************************** * vim:set shiftwidth=2 softtabstop=2 expandtab: * $Id: selftest_phy.c 5971 2010-03-06 06:44:56Z grg $ * * Module: selftest_phy.c * Project: NetFPGA selftest * Description: SATA selftest module * * Change history: * */ #include "../lib/C/reg_defines_selftest.h" #include "selftest.h" #include "selftest_phy.h" #include  #include  #define NUM_PORTS 4 static int prev_good_pkts[NUM_PORTS]; static int prev_bad_pkts[NUM_PORTS];1,1Top[?12l[?25h[?25l2[?12l[?25h[?25l3[?12l[?25h[?25l4[?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l9[?12l[?25h[?25l10,1[?12l[?25h[?25l1[?12l[?25h[?25l2,0-1[?12l[?25h[?25l3,1 [?12l[?25h[?25l4[?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8,0-1[?12l[?25h[?25l9,1 [?12l[?25h[?25l20,0-1[?12l[?25h[?25l1,1 [?12l[?25h[?25l/* * Reset the interface and configure it for continuous operation */ void phyResetContinuous(void) { int i; for (i = 0; i < NUM_PORTS; i++) { prev_good_pkts[i] = 0; prev_bad_pkts[i] = 0;32,16%[?12l[?25h[?25l1[?12l[?25h[?25l0[?12l[?25h[?25l29,0-1[?12l[?25h[?25l8,1 [?12l[?25h[?25l7[?12l[?25h[?25l6[?12l[?25h[?25l5[?12l[?25h[?25l4[?12l[?25h[?25l3,0-1[?12l[?25h[?25l2,1 [?12l[?25h[?25l1[?12l[?25h[?25l8[?12l[?25h[?25l12[?12l[?25h[?25l[]26[?12l[?25h[?25l[]12[?12l[?25h[?25l/\31,56%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_ERR_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INNST_OFFSET, &bad_pkts); printw(" Good: %d Bad: %d", good_pkts, bad_pkts); printw("\n"); // Verify if we should reset the counters /*if ((port_status & 0x1100) == 0x1100) { // Only reset if the number of good packets has incremented but the bad // packets have remained the same if (bad_pkts == prev_bad_pkts[i] && good_pkts != prev_good_pkts[i]) { writeReg(&nf2, PHY_TEST_PHY_0_RX_CTRL_REG + i * PHY_TEST_PHY_GROUP_INST__OFFSET, 0x3); } // Update the counters prev_bad_pkts[i] = bad_pkts; prev_good_pkts[i] = good_pkts; }*/ // Update the good flag if (bad_pkts != 0) good = 0;93,5661%[?12l[?25h[?25l/\99,761%[?12l[?25h[?25lsearch hit BOTTOM, continuing at TOP * */ #include "../lib/C/reg_defines_selftest.h" #include "selftest.h" #include "selftest_phy.h" #include  #include  #define NUM_PORTS 4 static int prev_good_pkts[NUM_PORTS]; static int prev_bad_pkts[NUM_PORTS]; /* * Reset the interface and configure it for continuous operation */ void phyResetContinuous(void) { int i; for (i = 0; i < NUM_PORTS; i++) { prev_good_pkts[i] = 0; prev_bad_pkts[i] = 0;21,126% search hit BOTTOM, continuing at TOP21,126%[?12l[?25h[?25l/\31,56%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_ERR_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INNST_OFFSET, &bad_pkts); printw(" Good: %d Bad: %d", good_pkts, bad_pkts); printw("\n"); // Verify if we should reset the counters /*if ((port_status & 0x1100) == 0x1100) { // Only reset if the number of good packets has incremented but the bad // packets have remained the same if (bad_pkts == prev_bad_pkts[i] && good_pkts != prev_good_pkts[i]) { writeReg(&nf2, PHY_TEST_PHY_0_RX_CTRL_REG + i * PHY_TEST_PHY_GROUP_INST__OFFSET, 0x3); } // Update the counters prev_bad_pkts[i] = bad_pkts; prev_good_pkts[i] = good_pkts; }*/ // Update the good flag if (bad_pkts != 0) good = 0;93,5661%[?12l[?25h[?25l/\99,761%[?12l[?25h[?25lsearch hit BOTTOM, continuing at TOP * */ #include "../lib/C/reg_defines_selftest.h" #include "selftest.h" #include "selftest_phy.h" #include  #include  #define NUM_PORTS 4 static int prev_good_pkts[NUM_PORTS]; static int prev_bad_pkts[NUM_PORTS]; /* * Reset the interface and configure it for continuous operation */ void phyResetContinuous(void) { int i; for (i = 0; i < NUM_PORTS; i++) { prev_good_pkts[i] = 0; prev_bad_pkts[i] = 0;21,126% search hit BOTTOM, continuing at TOP21,126%[?12l[?25h[?25l2[?12l[?25h[?25l3,0-1[?12l[?25h[?25l4,2 [?12l[?25h[?25l5,12[?12l[?25h[?25l6,3 [?12l[?25h[?25l7,12[?12l[?25h[?25l8,8 [?12l[?25h[?25l9,0-1[?12l[?25h[?25l30,12 [?12l[?25h[?25l1[?12l[?25h[?25l2[?12l[?25h[?25l { }33,37%[?12l[?25h[?25l {}34,0-18%[?12l[?25h[?25l  // Stop the test (and wait for the test to stop)35,128%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_CTRL_REG, 0x0);36,129%[?12l[?25h[?25l  sleep(1);37,1110%[?12l[?25h[?25l 38,0-111%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_PATTERN_REG, PHY_TEST_PATTERN_ENABLE_MASK);39,1211%[?12l[?25h[?25l 40,0-112%[?12l[?25h[?25l  // Start the test41,1213%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_CTRL_REG, PHY_TEST_CTRL_REPEAT);42,1214%[?12l[?25h[?25l } // phyResetContinuous43,1214%[?12l[?25h[?25l 44,0-115%[?12l[?25h[?25l /*45,216%[?12l[?25h[?25l  * Show the status of the SATA test when running in continuous mode46,1217%[?12l[?25h[?25l  *47,217%[?12l[?25h[?25l  * Return -- boolean indicating success48,1218%[?12l[?25h[?25l  */49,319%[?12l[?25h[?25l int phyShowStatusContinuous(void) {50,1220%[?12l[?25h[?25l  unsigned int val;51,1220%[?12l[?25h[?25l  unsigned int port_status;52,1221%[?12l[?25h[?25l  unsigned int good_pkts;53,1222%[?12l[?25h[?25l2[?12l[?25h[?25l1[?12l[?25h[?25l0[?12l[?25h[?25l49,3 [?12l[?25h[?25l8,12[?12l[?25h[?25l7,2 [?12l[?25h[?25l6,12[?12l[?25h[?25l5,2 [?12l[?25h[?25l4,0-1[?12l[?25h[?25l5,2 [?12l[?25h[?25l6,12[?12l[?25h[?25l7,2 [?12l[?25h[?25l8,12[?12l[?25h[?25l9,3 [?12l[?25h[?25l50,12[?12l[?25h[?25l1[?12l[?25h[?25l2[?12l[?25h[?25l3[?12l[?25h[?25l  unsigned int bad_pkts;54,1223%[?12l[?25h[?25l 55,0-123%[?12l[?25h[?25l  int i;56,824%[?12l[?25h[?25l 57,0-125%[?12l[?25h[?25l  int x, y;58,1126%[?12l[?25h[?25l 59,0-126%[?12l[?25h[?25l  int good = 1;60,1227%[?12l[?25h[?25l 61,0-128%[?12l[?25h[?25l  // Store the current screen position62,1229%[?12l[?25h[?25l  getyx(stdscr, y, x);63,1229%[?12l[?25h[?25l 64,0-130%[?12l[?25h[?25l  // Move down a line65,1231%[?12l[?25h[?25l  move(y + 1, x);66,1232%[?12l[?25h[?25l 67,0-132%[?12l[?25h[?25l  // Read the individual port registers68,1233%[?12l[?25h[?25l  for (i = 0; i < NUM_PORTS; i++) {69,1234%[?12l[?25h[?25l  printw(" Port %d:", i + 1);70,1235%[?12l[?25h[?25l 71,0-135%[?12l[?25h[?25l  // Start with the status register72,1236%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_STATUS_REG + i * PHY_TEST_PHY_GROUP_INST_OFFFSET, &port_status);73,1237%[?12l[?25h[?25l (FFS) if (port_status & 0x100) {74,1238%[?12l[?25h[?25l  printw(" link w/ %d", (port_status & 0xf0000) >> 16);75,1239%[?12l[?25h[?25l { }76,540%[?12l[?25h[?25l {} else {77,1040%[?12l[?25h[?25l  printw(" no link");78,1241%[?12l[?25h[?25l  good = 0;79,1242%[?12l[?25h[?25l { }80,542%[?12l[?25h[?25l {}81,0-143%[?12l[?25h[?25l  // Read the number of good/bad packets82,1244%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_GOOD_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INNST_OFFSET, &good_pkts);83,1245%[?12l[?25h[?25l(NNS) readReg(&nf2, PHY_TEST_PHY_0_RX_ERR_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INNST_OFFSET, &bad_pkts);84,1246%[?12l[?25h[?25l (NNS) printw(" Good: %d Bad: %d", good_pkts, bad_pkts);85,1247%[?12l[?25h[?25l 86,0-148%[?12l[?25h[?25l  printw("\n");87,1248%[?12l[?25h[?25l 88,0-149%[?12l[?25h[?25l  // Verify if we should reset the counters89,1250%[?12l[?25h[?25l  /*if ((port_status & 0x1100) == 0x1100) {90,1251%[?12l[?25h[?25l  // Only reset if the number of good packets has incremented but the bad91,1251%[?12l[?25h[?25l  // packets have remained the same92,1252%[?12l[?25h[?25l if (bad_pkts == prev_bad_pkts[i] && good_pkts != prev_good_pkts[i]) { writeReg(&nf2, PHY_TEST_PHY_0_RX_CTRL_REG + i * PHY_TEST_PHY_GROUP_INST_@ 93,1253%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_PHY_0_RX_CTRL_REG + i * PHY_TEST_PHY_GROUP_INST__OFFSET, 0x3);94,1254%[?12l[?25h[?25l {  }95,754%[?12l[?25h[?25l {}96,0-155%[?12l[?25h[?25l  // Update the counters97,1256%[?12l[?25h[?25l  prev_bad_pkts[i] = bad_pkts;98,1256%[?12l[?25h[?25l  prev_good_pkts[i] = good_pkts;99,1257%[?12l[?25h[?25l  }*/100,758%[?12l[?25h[?25l 101,0-159%[?12l[?25h[?25l  // Update the good flag102,1259%[?12l[?25h[?25l if (bad_pkts != 0) good = 0;103,1261%[?12l[?25h[?25l4[?12l[?25h[?25l }105,362%[?12l[?25h[?25l6,0-1[?12l[?25h[?25l  // Print overall success/failure107,1262%[?12l[?25h[?25l  move(y, x);108,1263%[?12l[?25h[?25l (y, x) printw("PHY test: %s", good ? "pass" : "fail");109,1264%[?12l[?25h[?25l  move(y + 1 + NUM_PORTS, x);110,1265%[?12l[?25h[?25l 111,0-165%[?12l[?25h[?25l  return good;112,1266%[?12l[?25h[?25l } // phyShowStatusContinuous113,1267%[?12l[?25h[?25l 114,0-168%[?12l[?25h[?25l /*115,268%[?12l[?25h[?25l * Stop the interface */116,1270%[?12l[?25h[?25l7,3 [?12l[?25h[?25l void phyStopContinuous(void) {118,1270%[?12l[?25h[?25l7,3 [?12l[?25h[?25l6,12[?12l[?25h[?25l5,2 [?12l[?25h[?25l4,0-1[?12l[?25h[?25l3,12 [?12l[?25h[?25l2[?12l[?25h[?25l1,0-1[?12l[?25h[?25l0,12 [?12l[?25h[?25l09[?12l[?25h[?25l(y, x)8[?12l[?25h[?25l(y, x)7[?12l[?25h[?25l6,0-1[?12l[?25h[?25l5,3 [?12l[?25h[?25l4,12[?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l1,0-1[?12l[?25h[?25l0,7 [?12l[?25h[?25l99,12[?12l[?25h[?25l8[?12l[?25h[?25l7[?12l[?25h[?25l6,0-1[?12l[?25h[?25l }95,770%[?12l[?25h[?25l writeReg(&nf2, PHY_TEST_PHY_0_RX_CTRL_REG + i * PHY_TEST_PHY_GROUP_INST__OFFSET, 0x3);94,1268%[?12l[?25h[?25l if (bad_pkts == prev_bad_pkts[i] && good_pkts != prev_good_pkts[i]) {93,1268%[?12l[?25h[?25l // packets have remained the same92,1267%[?12l[?25h[?25l // Only reset if the number of good packets has incremented but the bad91,1266%[?12l[?25h[?25l /*if ((port_status & 0x1100) == 0x1100) {90,1265%[?12l[?25h[?25l // Verify if we should reset the counters89,1265%[?12l[?25h[?25l88,0-164%[?12l[?25h[?25l printw("\n");87,1263%[?12l[?25h[?25l86,0-162%[?12l[?25h[?25l printw(" Good: %d Bad: %d", good_pkts, bad_pkts);85,1262%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_ERR_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INNST_OFFSET, &bad_pkts);84,1261%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_GOOD_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INNST_OFFSET, &good_pkts);(NNS)83,1259%[?12l[?25h[?25l // Read the number of good/bad packets(NNS)82,1259%[?12l[?25h[?25l81,0-158%[?12l[?25h[?25l }80,557%[?12l[?25h[?25l good = 0;79,1256%[?12l[?25h[?25l printw(" no link");78,1256%[?12l[?25h[?25l else {}77,1055%[?12l[?25h[?25l }{}76,554%[?12l[?25h[?25l printw(" link w/ %d", (port_status & 0xf0000) >> 16);75,1254%[?12l[?25h[?25l if (port_status & 0x100) {@ 74,1253%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_STATUS_REG + i * PHY_TEST_PHY_GROUP_INST_OFFFSET, &port_status);73,1252%[?12l[?25h[?25l // Start with the status register(FFS)72,1251%[?12l[?25h[?25l71,0-151%[?12l[?25h[?25l printw(" Port %d:", i + 1);70,1250%[?12l[?25h[?25l for (i = 0; i < NUM_PORTS; i++) {69,1249%[?12l[?25h[?25l // Read the individual port registers68,1248%[?12l[?25h[?25l67,0-148%[?12l[?25h[?25l move(y + 1, x);66,1247%[?12l[?25h[?25l // Move down a line65,1246%[?12l[?25h[?25l@ 64,0-145%[?12l[?25h[?25l getyx(stdscr, y, x);63,1245%[?12l[?25h[?25l // Store the current screen position@ 62,1244%[?12l[?25h[?25l61,0-144%[?12l[?25h[?25l int good = 1;60,1243%[?12l[?25h[?25l59,0-142%[?12l[?25h[?25l int x, y;58,1142%[?12l[?25h[?25l9,0-1[?12l[?25h[?25l60,12 [?12l[?25h[?25l1,0-1[?12l[?25h[?25l2,12 [?12l[?25h[?25l3[?12l[?25h[?25l4,0-1[?12l[?25h[?25l5,12 [?12l[?25h[?25l6[?12l[?25h[?25l7,0-1[?12l[?25h[?25l8,12 [?12l[?25h[?25l9[?12l[?25h[?25l70[?12l[?25h[?25l1,0-1[?12l[?25h[?25l2,12 [?12l[?25h[?25l(FFS)3[?12l[?25h[?25l(FFS)4[?12l[?25h[?25l5[?12l[?25h[?25l{}6,5 [?12l[?25h[?25l{}7,10[?12l[?25h[?25l8,12[?12l[?25h[?25l9[?12l[?25h[?25l { }80,542%[?12l[?25h[?25l {}81,0-143%[?12l[?25h[?25l  // Read the number of good/bad packets82,1244%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_GOOD_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INNST_OFFSET, &good_pkts);83,1245%[?12l[?25h[?25l(NNS) readReg(&nf2, PHY_TEST_PHY_0_RX_ERR_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INNST_OFFSET, &bad_pkts);84,1246%[?12l[?25h[?25l (NNS) printw(" Good: %d Bad: %d", good_pkts, bad_pkts);85,1247%[?12l[?25h[?25l 86,0-148%[?12l[?25h[?25l  printw("\n");87,1248%[?12l[?25h[?25l 88,0-149%[?12l[?25h[?25l  // Verify if we should reset the counters89,1250%[?12l[?25h[?25l  /*if ((port_status & 0x1100) == 0x1100) {90,1251%[?12l[?25h[?25l  // Only reset if the number of good packets has incremented but the bad91,1251%[?12l[?25h[?25l  // packets have remained the same92,1252%[?12l[?25h[?25l if (bad_pkts == prev_bad_pkts[i] && good_pkts != prev_good_pkts[i]) { writeReg(&nf2, PHY_TEST_PHY_0_RX_CTRL_REG + i * PHY_TEST_PHY_GROUP_INST_@ 93,1253%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_PHY_0_RX_CTRL_REG + i * PHY_TEST_PHY_GROUP_INST__OFFSET, 0x3);94,1254%[?12l[?25h[?25l {  }95,754%[?12l[?25h[?25l {}96,0-155%[?12l[?25h[?25l  // Update the counters97,1256%[?12l[?25h[?25l  prev_bad_pkts[i] = bad_pkts;98,1256%[?12l[?25h[?25l  prev_good_pkts[i] = good_pkts;99,1257%[?12l[?25h[?25l  }*/100,758%[?12l[?25h[?25l 101,0-159%[?12l[?25h[?25l  // Update the good flag102,1259%[?12l[?25h[?25l if (bad_pkts != 0) good = 0;103,1261%[?12l[?25h[?25l4[?12l[?25h[?25l }105,362%[?12l[?25h[?25l6,0-1[?12l[?25h[?25l  // Print overall success/failure107,1262%[?12l[?25h[?25l  move(y, x);108,1263%[?12l[?25h[?25l (y, x) printw("PHY test: %s", good ? "pass" : "fail");109,1264%[?12l[?25h[?25l  move(y + 1 + NUM_PORTS, x);110,1265%[?12l[?25h[?25l 111,0-165%[?12l[?25h[?25l  return good;112,1266%[?12l[?25h[?25l } // phyShowStatusContinuous113,1267%[?12l[?25h[?25l 114,0-168%[?12l[?25h[?25l /*115,268%[?12l[?25h[?25l * Stop the interface */116,1270%[?12l[?25h[?25l7,3 [?12l[?25h[?25l void phyStopContinuous(void) {118,1270%[?12l[?25h[?25l  // Stop the test (and wait for the test to stop)119,1271%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_CTRL_REG, 0x00000000);120,1272%[?12l[?25h[?25l } // phyStopContinuous121,1273%[?12l[?25h[?25l 122,0-173%[?12l[?25h[?25l /*123,274%[?12l[?25h[?25l  * Get the result of the test124,1275%[?12l[?25h[?25l  *125,276%[?12l[?25h[?25l  * Return -- boolean indicating success126,1276%[?12l[?25h[?25l  */127,377%[?12l[?25h[?25l int phyGetResult(void) {128,1278%[?12l[?25h[?25l  unsigned int val;129,1279%[?12l[?25h[?25l  unsigned int port_status;130,1279%[?12l[?25h[?25l  unsigned int good_pkts;131,1280%[?12l[?25h[?25l  unsigned int bad_pkts;132,1281%[?12l[?25h[?25l 133,0-182%[?12l[?25h[?25l  int i;134,882%[?12l[?25h[?25l 135,0-183%[?12l[?25h[?25l  int good = 1;136,1284%[?12l[?25h[?25l 137,0-185%[?12l[?25h[?25l  // Read the individual port registers138,1285%[?12l[?25h[?25l  for (i = 0; i < NUM_PORTS; i++) {139,1286%[?12l[?25h[?25l  // Start with the status register140,1287%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_STATUS_REG + i * PHY_TEST_PHY_GROUP_INST_OFFFSET, &port_status);141,1288%[?12l[?25h[?25l (FFS) if ((port_status & 0x100) == 0) {142,1288%[?12l[?25h[?25l  good = 0;143,1289%[?12l[?25h[?25l { }144,590%[?12l[?25h[?25l {}145,0-191%[?12l[?25h[?25l  // Read the number of good/bad packets146,1291%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_GOOD_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INNST_OFFSET, &good_pkts);147,1292%[?12l[?25h[?25l(NNS) readReg(&nf2, PHY_TEST_PHY_0_RX_ERR_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INSST_OFFSET, &bad_pkts);148,1293%[?12l[?25h[?25l (SST)149,0-194%[?12l[?25h[?25l  // Update the good flag150,1294%[?12l[?25h[?25l  if (bad_pkts != 0) {151,1295%[?12l[?25h[?25l  good = 0;152,1296%[?12l[?25h[?25l { }153,597%[?12l[?25h[?25l {{} }154,397%[?12l[?25h[?25l {}155,0-198%[?12l[?25h[?25l  return good;156,1299%[?12l[?25h[?25l } // phyGetResult157,12Bot[?12l[?25h[?25l:[?12l[?25hq[?25l[?12l[?25h[?25l[?12l[?25h [?25l157,12Bot[?12l[?25h[?25l6[?12l[?25h[?25l5,0-1[?12l[?25h[?25l{}4,3 [?12l[?25h[?25l{{} }3,5[?12l[?25h[?25l{}2,12[?12l[?25h[?25l1[?12l[?25h[?25l0[?12l[?25h[?25l49,0-1[?12l[?25h[?25l(SST)8,12 [?12l[?25h[?25l(NNS)(SST)7[?12l[?25h[?25l(NNS)6[?12l[?25h[?25l5,0-1[?12l[?25h[?25l{}4,5 [?12l[?25h[?25l{}3,12[?12l[?25h[?25l2[?12l[?25h[?25l(FFS)1[?12l[?25h[?25l(FFS)0[?12l[?25h[?25l39[?12l[?25h[?25l8[?12l[?25h[?25l137,0-199%[?12l[?25h[?25l int good = 1;136,1298%[?12l[?25h[?25l135,0-197%[?12l[?25h[?25l int i;134,897%[?12l[?25h[?25l133,0-196%[?12l[?25h[?25l unsigned int bad_pkts;132,1295%[?12l[?25h[?25l unsigned int good_pkts;131,1294%[?12l[?25h[?25l unsigned int port_status;130,1294%[?12l[?25h[?25l unsigned int val;129,1293%[?12l[?25h[?25lint phyGetResult(void) {@ 128,1292%[?12l[?25h[?25l */127,392%[?12l[?25h[?25l * Return -- boolean indicating success@ 126,1291%[?12l[?25h[?25l *125,291%[?12l[?25h[?25l * Get the result of the test124,1291%[?12l[?25h[?25l/*123,290%[?12l[?25h[?25l122,0-189%[?12l[?25h[?25l} // phyStopContinuous121,1288%[?12l[?25h[?25l writeReg(&nf2, PHY_TEST_CTRL_REG, 0x00000000);120,1288%[?12l[?25h[?25l // Stop the test (and wait for the test to stop)@ 119,1287%[?12l[?25h[?25lvoid phyStopContinuous(void) {118,1287%[?12l[?25h[?25l */117,386%[?12l[?25h[?25l * Stop the interface116,1285%[?12l[?25h[?25l:[?12l[?25h1[?25l[?12l[?25h [?25l/* **************************************************************************** * vim:set shiftwidth=2 softtabstop=2 expandtab: * $Id: selftest_phy.c 5971 2010-03-06 06:44:56Z grg $ * * Module: selftest_phy.c * Project: NetFPGA selftest * Description: SATA selftest module * * Change history: * */ #include "../lib/C/reg_defines_selftest.h" #include "selftest.h" #include "selftest_phy.h" #include  #include  #define NUM_PORTS 4 static int prev_good_pkts[NUM_PORTS]; static int prev_bad_pkts[NUM_PORTS];1,1Top[?12l[?25h[?25l2[?12l[?25h[?25l3[?12l[?25h[?25l4[?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l9[?12l[?25h[?25l10,1[?12l[?25h[?25l1[?12l[?25h[?25l2,0-1[?12l[?25h[?25l3,1 [?12l[?25h[?25l4[?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8,0-1[?12l[?25h[?25l9,1 [?12l[?25h[?25l20,0-1[?12l[?25h[?25l1,1 [?12l[?25h[?25l2[?12l[?25h[?25l3,0-1[?12l[?25h[?25l /*24,10%[?12l[?25h[?25l  * Reset the interface and configure it for continuous operation25,11%[?12l[?25h[?25l  */26,12%[?12l[?25h[?25l void phyResetContinuous(void) {27,12%[?12l[?25h[?25l  int i;28,13%[?12l[?25h[?25l 29,0-14%[?12l[?25h[?25l  for (i = 0; i < NUM_PORTS; i++) {30,15%[?12l[?25h[?25l  prev_good_pkts[i] = 0;31,15%[?12l[?25h[?25l  prev_bad_pkts[i] = 0;32,16%[?12l[?25h[?25l  }33,17%[?12l[?25h[?25l 34,0-18%[?12l[?25h[?25l  // Stop the test (and wait for the test to stop)35,18%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_CTRL_REG, 0x0);36,19%[?12l[?25h[?25l  sleep(1);37,110%[?12l[?25h[?25l 38,0-111%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_PATTERN_REG, PHY_TEST_PATTERN_ENABLE_MASK);39,111%[?12l[?25h[?25l 40,0-112%[?12l[?25h[?25l:[?12l[?25h1[?25l[?12l[?25h [?25l/* **************************************************************************** * vim:set shiftwidth=2 softtabstop=2 expandtab: * $Id: selftest_phy.c 5971 2010-03-06 06:44:56Z grg $ * * Module: selftest_phy.c * Project: NetFPGA selftest * Description: SATA selftest module * * Change history: * */ #include "../lib/C/reg_defines_selftest.h" #include "selftest.h" #include "selftest_phy.h" #include  #include 1,1Top[?12l[?25h[?25l2[?12l[?25h[?25l3[?12l[?25h[?25l4[?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l9[?12l[?25h[?25l10,1[?12l[?25h[?25l1[?12l[?25h[?25l2,0-1[?12l[?25h[?25l3,1 [?12l[?25h[?25l4[?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8,0-1[?12l[?25h[?25l9,1 [?12l[?25h[?25l20,0-1[?12l[?25h[?25l1,1 [?12l[?25h[?25l2[?12l[?25h[?25l3,0-1[?12l[?25h[?25l /*24,10%[?12l[?25h[?25l  * Reset the interface and configure it for continuous operation25,11%[?12l[?25h[?25l  */26,12%[?12l[?25h[?25l void phyResetContinuous(void) {27,12%[?12l[?25h[?25l  int i;28,13%[?12l[?25h[?25l 29,0-14%[?12l[?25h[?25l  for (i = 0; i < NUM_PORTS; i++) {30,15%[?12l[?25h[?25l  prev_good_pkts[i] = 0;31,15%[?12l[?25h[?25l  prev_bad_pkts[i] = 0;32,16%[?12l[?25h[?25l  }33,17%[?12l[?25h[?25l 34,0-18%[?12l[?25h[?25l  // Stop the test (and wait for the test to stop)35,18%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_CTRL_REG, 0x0);36,19%[?12l[?25h[?25l  sleep(1);37,110%[?12l[?25h[?25l 38,0-111%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_PATTERN_REG, PHY_TEST_PATTERN_ENABLE_MASK);39,111%[?12l[?25h[?25l 40,0-112%[?12l[?25h[?25l  // Start the test41,113%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_CTRL_REG, PHY_TEST_CTRL_REPEAT);42,114%[?12l[?25h[?25l {} // phyResetContinuous43,114%[?12l[?25h[?25l {}44,0-115%[?12l[?25h[?25l /*45,116%[?12l[?25h[?25l  * Show the status of the SATA test when running in continuous mode46,117%[?12l[?25h[?25l  *47,117%[?12l[?25h[?25l  * Return -- boolean indicating success48,118%[?12l[?25h[?25l  */49,119%[?12l[?25h[?25l int phyShowStatusContinuous(void) {50,120%[?12l[?25h[?25l  unsigned int val;51,120%[?12l[?25h[?25l  unsigned int port_status;52,121%[?12l[?25h[?25l  unsigned int good_pkts;53,122%[?12l[?25h[?25l  unsigned int bad_pkts;54,123%[?12l[?25h[?25l 55,0-123%[?12l[?25h[?25l  int i;56,124%[?12l[?25h[?25l 57,0-125%[?12l[?25h[?25l  int x, y;58,126%[?12l[?25h[?25l 59,0-126%[?12l[?25h[?25l  int good = 1;60,127%[?12l[?25h[?25l 61,0-128%[?12l[?25h[?25l  // Store the current screen position62,129%[?12l[?25h[?25l  getyx(stdscr, y, x);63,129%[?12l[?25h[?25l 64,0-130%[?12l[?25h[?25l  // Move down a line65,131%[?12l[?25h[?25l  move(y + 1, x);66,132%[?12l[?25h[?25l 67,0-132%[?12l[?25h[?25l  // Read the individual port registers68,133%[?12l[?25h[?25l  for (i = 0; i < NUM_PORTS; i++) {69,134%[?12l[?25h[?25l  printw(" Port %d:", i + 1);70,135%[?12l[?25h[?25l 71,0-135%[?12l[?25h[?25l  // Start with the status register72,136%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_STATUS_REG + i * PHY_TEST_PHY_GROUP_INST_OFFFSET, &port_status);73,137%[?12l[?25h[?25l  if (port_status & 0x100) {74,138%[?12l[?25h[?25l  printw(" link w/ %d", (port_status & 0xf0000) >> 16);75,139%[?12l[?25h[?25l  }76,140%[?12l[?25h[?25l  else {77,140%[?12l[?25h[?25l  printw(" no link");78,141%[?12l[?25h[?25l  good = 0;79,142%[?12l[?25h[?25l  }80,142%[?12l[?25h[?25l 81,0-143%[?12l[?25h[?25l  // Read the number of good/bad packets82,144%[?12l[?25h[?25l:[?12l[?25hq[?25l[?12l[?25h [?25l[?1l>[?12l[?25h[?1049l]0;root@node1-1: ~/netfpga/projects/selftest/swroot@node1-1:~/netfpga/projects/selftest/sw# vi selftest_phy.c ./selftest -n Found net device: nf2c0 CPCI Information ---------------- Version: 4 (rev 1) Device (Virtex) Information --------------------------- Project directory: selftest Project name: Selftest Project description: NetFPGA selftest -- exercises all major subsystems of the board Device ID: 5 Version: 1.1.0 Built against CPCI version: 4 (rev 1) NetFPGA selftest 1.00 alpha Running..... FAILED. Failing tests: PHY interface ]0;root@node1-1: ~/netfpga/projects/selftest/swroot@node1-1:~/netfpga/projects/selftest/sw# ./selftest -nvi selftest_phy.c [?1049h[?1h=[?12;25h[?12l[?25h[?25l"selftest_phy.c" 157L, 3955C[>c/* **************************************************************************** * vim:set shiftwidth=2 softtabstop=2 expandtab: * $Id: selftest_phy.c 5971 2010-03-06 06:44:56Z grg $ * * Module: selftest_phy.c * Project: NetFPGA selftest * Description: SATA selftest module * * Change history: * */ #include "../lib/C/reg_defines_selftest.h" #include "selftest.h" #include "selftest_phy.h" #include  #include  #define NUM_PORTS 4 static int prev_good_pkts[NUM_PORTS]; static int prev_bad_pkts[NUM_PORTS];1,1Top[?12l[?25hP+q436f\P+q6b75\P+q6b64\P+q6b72\P+q6b6c\P+q2332\P+q2334\P+q2569\P+q2a37\P+q6b31\P+q6b32\[?25l/* **************************************************************************** * vim:set shiftwidth=2 softtabstop=2 expandtab: * $Id: selftest_phy.c 5971 2010-03-06 06:44:56Z grg $ * * Module: selftest_phy.c * Project: NetFPGA selftest * Description: SATA selftest module * * Change history: * */ #include "../lib/C/reg_defines_selftest.h" #include "selftest.h" #include "selftest_phy.h" #include  #include  #define NUM_PORTS 4 static int prev_good_pkts[NUM_PORTS]; static int prev_bad_pkts[NUM_PORTS];1,1Top "selftest_phy.c" 157L, 3955C1,1Top[?12l[?25hP+q6b33\[?25l[?12l[?25hP+q6b34\P+q6b35\P+q6b36\P+q6b37\P+q6b38\P+q6b39\P+q6b3b\P+q4631\P+q4632\P+q2531\P+q2638\P+q6b62\P+q6b49\P+q6b44\P+q6b68\P+q4037\P+q6b50\P+q6b4e\P+q4b31\P+q4b33\P+q4b34\P+q4b35\P+q6b42\[?25l2[?12l[?25h[?25l3[?12l[?25h[?25l4[?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l9[?12l[?25h[?25l10,1[?12l[?25h[?25l1[?12l[?25h[?25l2,0-1[?12l[?25h[?25l3,1 [?12l[?25h[?25l4[?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8,0-1[?12l[?25h[?25l9,1 [?12l[?25h[?25l20,0-1[?12l[?25h[?25l1,1 [?12l[?25h[?25l2[?12l[?25h[?25l3,0-1[?12l[?25h[?25l /*24,10%[?12l[?25h[?25l  * Reset the interface and configure it for continuous operation25,11%[?12l[?25h[?25l  */26,12%[?12l[?25h[?25l void phyResetContinuous(void) {27,12%[?12l[?25h[?25l  int i;28,13%[?12l[?25h[?25l 29,0-14%[?12l[?25h[?25l  for (i = 0; i < NUM_PORTS; i++) {30,15%[?12l[?25h[?25l  prev_good_pkts[i] = 0;31,15%[?12l[?25h[?25l  prev_bad_pkts[i] = 0;32,16%[?12l[?25h[?25l  }33,17%[?12l[?25h[?25l 34,0-18%[?12l[?25h[?25l  // Stop the test (and wait for the test to stop)35,18%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_CTRL_REG, 0x0);36,19%[?12l[?25h[?25l  sleep(1);37,110%[?12l[?25h[?25l 38,0-111%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_PATTERN_REG, PHY_TEST_PATTERN_ENABLE_MASK);39,111%[?12l[?25h[?25l 40,0-112%[?12l[?25h[?25l  // Start the test41,113%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_CTRL_REG, PHY_TEST_CTRL_REPEAT);42,114%[?12l[?25h[?25l {} // phyResetContinuous43,114%[?12l[?25h[?25l {}44,0-115%[?12l[?25h[?25l /*45,116%[?12l[?25h[?25l  * Show the status of the SATA test when running in continuous mode46,117%[?12l[?25h[?25l  *47,117%[?12l[?25h[?25l  * Return -- boolean indicating success48,118%[?12l[?25h[?25l  */49,119%[?12l[?25h[?25l int phyShowStatusContinuous(void) {50,120%[?12l[?25h[?25l  unsigned int val;51,120%[?12l[?25h[?25l  unsigned int port_status;52,121%[?12l[?25h[?25l  unsigned int good_pkts;53,122%[?12l[?25h[?25l  unsigned int bad_pkts;54,123%[?12l[?25h[?25l 55,0-123%[?12l[?25h[?25l  int i;56,124%[?12l[?25h[?25l 57,0-125%[?12l[?25h[?25l  int x, y;58,126%[?12l[?25h[?25l 59,0-126%[?12l[?25h[?25l  int good = 1;60,127%[?12l[?25h[?25l 61,0-128%[?12l[?25h[?25l  // Store the current screen position62,129%[?12l[?25h[?25l  getyx(stdscr, y, x);63,129%[?12l[?25h[?25l 64,0-130%[?12l[?25h[?25l  // Move down a line65,131%[?12l[?25h[?25l  move(y + 1, x);66,132%[?12l[?25h[?25l 67,0-132%[?12l[?25h[?25l  // Read the individual port registers68,133%[?12l[?25h[?25l  for (i = 0; i < NUM_PORTS; i++) {69,134%[?12l[?25h[?25l  printw(" Port %d:", i + 1);70,135%[?12l[?25h[?25l 71,0-135%[?12l[?25h[?25l  // Start with the status register72,136%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_STATUS_REG + i * PHY_TEST_PHY_GROUP_INST_OFFFSET, &port_status);73,137%[?12l[?25h[?25l  if (port_status & 0x100) {74,138%[?12l[?25h[?25l  printw(" link w/ %d", (port_status & 0xf0000) >> 16);75,139%[?12l[?25h[?25l  }76,140%[?12l[?25h[?25l  else {77,140%[?12l[?25h[?25l  printw(" no link");78,141%[?12l[?25h[?25l  good = 0;79,142%[?12l[?25h[?25l8[?12l[?25h[?25l7[?12l[?25h[?25l6[?12l[?25h[?25l5[?12l[?25h[?25l4[?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l1,0-1[?12l[?25h[?25l0,1 [?12l[?25h[?25l69[?12l[?25h[?25l8[?12l[?25h[?25l7,0-1[?12l[?25h[?25l6,1 [?12l[?25h[?25l5[?12l[?25h[?25l4,0-1[?12l[?25h[?25l3,1 [?12l[?25h[?25l2[?12l[?25h[?25l1,0-1[?12l[?25h[?25l0,1 [?12l[?25h[?25l59,0-1[?12l[?25h[?25l8,1 [?12l[?25h[?25l57,0-141%[?12l[?25h[?25l int i;56,140%[?12l[?25h[?25l55,0-140%[?12l[?25h[?25l unsigned int bad_pkts;54,139%[?12l[?25h[?25l unsigned int good_pkts;53,138%[?12l[?25h[?25l unsigned int port_status;52,137%[?12l[?25h[?25l unsigned int val;@ 51,137%[?12l[?25h[?25lint phyShowStatusContinuous(void) {50,136%[?12l[?25h[?25l */49,135%[?12l[?25h[?25l * Return -- boolean indicating success48,135%[?12l[?25h[?25l *47,134%[?12l[?25h[?25l * Show the status of the SATA test when running in continuous mode46,133%[?12l[?25h[?25l/*45,132%[?12l[?25h[?25l44,0-132%[?12l[?25h[?25l} // phyResetContinuous43,131%[?12l[?25h[?25l writeReg(&nf2, PHY_TEST_CTRL_REG, PHY_TEST_CTRL_REPEAT);42,130%[?12l[?25h[?25l // Start the test41,129%[?12l[?25h[?25l40,0-129%[?12l[?25h[?25l writeReg(&nf2, PHY_TEST_PATTERN_REG, PHY_TEST_PATTERN_ENABLE_MASK);39,128%[?12l[?25h[?25l38,0-127%[?12l[?25h[?25l sleep(1);37,126%[?12l[?25h[?25l writeReg(&nf2, PHY_TEST_CTRL_REG, 0x0);36,126%[?12l[?25h[?25l // Stop the test (and wait for the test to stop)35,125%[?12l[?25h[?25l34,0-124%[?12l[?25h[?25l }33,123%[?12l[?25h[?25l prev_bad_pkts[i] = 0;32,123%[?12l[?25h[?25l prev_good_pkts[i] = 0;31,122%[?12l[?25h[?25l for (i = 0; i < NUM_PORTS; i++) {30,121%[?12l[?25h[?25l29,0-120%[?12l[?25h[?25l int i;28,120%[?12l[?25h[?25lvoid phyResetContinuous(void) {27,119%[?12l[?25h[?25l */26,118%[?12l[?25h[?25l * Reset the interface and configure it for continuous operation25,117%[?12l[?25h[?25l/*24,117%[?12l[?25h[?25l23,0-116%[?12l[?25h[?25lstatic int prev_bad_pkts[NUM_PORTS];22,115%[?12l[?25h[?25lstatic int prev_good_pkts[NUM_PORTS];21,114%[?12l[?25h[?25l20,0-114%[?12l[?25h[?25l#define NUM_PORTS 419,113%[?12l[?25h[?25l18,0-112%[?12l[?25h[?25l#include 17,111%[?12l[?25h[?25l#include 16,111%[?12l[?25h[?25l#include "selftest_phy.h"15,110%[?12l[?25h[?25l#include "selftest.h"14,19%[?12l[?25h[?25l#include "../lib/C/reg_defines_selftest.h"13,18%[?12l[?25h[?25l12,0-18%[?12l[?25h[?25l */11,17%[?12l[?25h[?25l *10,16%[?12l[?25h[?25l * Change history:9,15%[?12l[?25h[?25l *8,15%[?12l[?25h[?25l * Description: SATA selftest module7,14%[?12l[?25h[?25l * Project: NetFPGA selftest6,13%[?12l[?25h[?25l * Module: selftest_phy.c5,12%[?12l[?25h[?25l *4,12%[?12l[?25h[?25l:[?12l[?25he[?25l[?12l[?25h[?25l [?12l[?25hs[?25l[?12l[?25he[?25l[?12l[?25hl[?25l[?12l[?25hf[?25l[?12l[?25ht[?25l[?12l[?25he[?25l[?12l[?25hs[?25l[?12l[?25ht[?25l[?12l[?25h.[?25l[?12l[?25hh[?25l[?12l[?25h [?25l"selftest.h" 38L, 859C/* **************************************************************************** * vim:set shiftwidth=2 softtabstop=2 expandtab: * $Id: selftest.h 2016 2007-07-24 20:24:15Z grg $ Module: selftest.h * Project: NetFPGA selftest software * Description: * Change history: * */ifndef _SELFTEST_H #define _SELFTEST_H 1 /* * The NF2 structure for all files to use */extern struct nf2device nf2; Define a structure for a test interface1,1Top[?12l[?25h[?25l2[?12l[?25h[?25l3[?12l[?25h[?25l4[?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l9[?12l[?25h[?25l10,1[?12l[?25h[?25l1[?12l[?25h[?25l2,0-1[?12l[?25h[?25l3,1 [?12l[?25h[?25l4[?12l[?25h[?25l5,0-1[?12l[?25h[?25l6,1 [?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l9[?12l[?25h[?25l20,0-1[?12l[?25h[?25l1,1 [?12l[?25h[?25l2[?12l[?25h[?25l3[?12l[?25h[?25l  * Fields:24,16%[?12l[?25h[?25l  * name : module name25,113%[?12l[?25h[?25l  * reset_continuous : reset the interface and prepare for continuous testing26,120%[?12l[?25h[?25l  * mode27,126%[?12l[?25h[?25l  * show_status_continuous : show the status of the continuous test28,133%[?12l[?25h[?25l  */29,140%[?12l[?25h[?25l struct test_module {30,146%[?12l[?25h[?25l  char *name;31,153%[?12l[?25h[?25l  void (*reset_continuous) (void);32,160%[?12l[?25h[?25l  int (*show_status_continuous) (void);33,166%[?12l[?25h[?25l  void (*stop_continuous) (void);34,173%[?12l[?25h[?25l  int (*get_result) (void);35,180%[?12l[?25h[?25l {};36,186%[?12l[?25h[?25l {}37,0-193%[?12l[?25h[?25l #endif38,1Bot[?12l[?25h[?25l7,0-1[?12l[?25h[?25l{}6,1 [?12l[?25h[?25l{}5[?12l[?25h[?25l4[?12l[?25h[?25l:[?12l[?25hb[?25l[?12l[?25hd[?25l[?12l[?25h [?25l"selftest_phy.c" 157L, 3955C **************************************************************************** * vim:set shiftwidth=2 softtabstop=2 expandtab: * $Id: selftest_phy.c 5971 2010-03-06 06:44:56Z grg $ * * Module: selftest_phy.c * Project: NetFPGA selftest * Description: SATA selftest module Change history:*/#include "../lib/C/reg_defines_selftest.h"#include "selftest.h" #include "selftest_phy.h" #include  #include #define NUM_PORTS 4static int prev_good_pkts[NUM_PORTS]; static int prev_bad_pkts[NUM_PORTS];4,1Top[?12l[?25h[?25l:[?12l[?25he[?25l[?12l[?25h[?25l [?12l[?25hs[?25l[?12l[?25he[?25l[?12l[?25hl[?25l[?12l[?25hf[?25l[?12l[?25h[?25l4,1Top[?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l9[?12l[?25h[?25l10,1[?12l[?25h[?25l1[?12l[?25h[?25l2,0-1[?12l[?25h[?25l3,1 [?12l[?25h[?25l4[?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8,0-1[?12l[?25h[?25l9,1 [?12l[?25h[?25l20,0-1[?12l[?25h[?25l19,1 [?12l[?25h[?25l2[?12l[?25h[?25l9[?12l[?25h[?25l/\21,27Top[?12l[?25h[?25l22,26Top[?12l[?25h[?25l/* * Reset the interface and configure it for continuous operation */ void phyResetContinuous(void) { int i; for (i = 0; i < NUM_PORTS; i++) {30,195%[?12l[?25h[?25l  prev_good_pkts[i] = 0;31,195%[?12l[?25h[?25l [i] prev_bad_pkts[i] = 0;32,196%[?12l[?25h[?25l { }33,37%[?12l[?25h[?25l {}34,0-18%[?12l[?25h[?25l  // Stop the test (and wait for the test to stop)35,198%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_CTRL_REG, 0x0);36,199%[?12l[?25h[?25l /\ int x, y; int good = 1; // Store the current screen position getyx(stdscr, y, x); // Move down a line move(y + 1, x); // Read the individual port registers for (i = 0; i < NUM_PORTS; i++) { printw(" Port %d:", i + 1); // Start with the status register readReg(&nf2, PHY_TEST_PHY_0_RX_STATUS_REG + i * PHY_TEST_PHY_GROUP_INST_OFFFSET, &port_status); if (port_status & 0x100) { printw(" link w/ %d", (port_status & 0xf0000) >> 16); } else { printw(" no link"); good = 0;69,1942%[?12l[?25h[?25l8[?12l[?25h[?25l7,0-1[?12l[?25h[?25l6,17 [?12l[?25h[?25l5,19[?12l[?25h[?25l4,0-1[?12l[?25h[?25l3,19 [?12l[?25h[?25l2[?12l[?25h[?25l1,0-1[?12l[?25h[?25l0,15 [?12l[?25h[?25l59,0-1[?12l[?25h[?25l8,11 [?12l[?25h[?25l57,0-141%[?12l[?25h[?25l int i;56,840%[?12l[?25h[?25l55,0-140%[?12l[?25h[?25l unsigned int bad_pkts;54,1939%[?12l[?25h[?25l unsigned int good_pkts;53,1938%[?12l[?25h[?25l unsigned int port_status;52,1937%[?12l[?25h[?25l unsigned int val;@ 51,1937%[?12l[?25h[?25l2[?12l[?25h[?25l3[?12l[?25h[?25l4[?12l[?25h[?25l5,0-1[?12l[?25h[?25l6,8 [?12l[?25h[?25l7,0-1[?12l[?25h[?25l8,11 [?12l[?25h[?25l9,0-1[?12l[?25h[?25l60,15 [?12l[?25h[?25l1,0-1[?12l[?25h[?25l2,19 [?12l[?25h[?25l3[?12l[?25h[?25l4,0-1[?12l[?25h[?25l5,19 [?12l[?25h[?25l6,17[?12l[?25h[?25l7,0-1[?12l[?25h[?25l8,19 [?12l[?25h[?25l9[?12l[?25h[?25l70[?12l[?25h[?25l1,0-1[?12l[?25h[?25l2,19 [?12l[?25h[?25l  readReg(&nf2, PHY_TEST_PHY_0_RX_STATUS_REG + i * PHY_TEST_PHY_GROUP_INST_OFFFSET, &port_status);73,1937%[?12l[?25h[?25l  if (port_status & 0x100) {74,1938%[?12l[?25h[?25l  printw(" link w/ %d", (port_status & 0xf0000) >> 16);75,1939%[?12l[?25h[?25l { }76,540%[?12l[?25h[?25l {} else {77,1040%[?12l[?25h[?25l  printw(" no link");78,1941%[?12l[?25h[?25l  good = 0;79,1542%[?12l[?25h[?25l { }80,542%[?12l[?25h[?25l {}81,0-143%[?12l[?25h[?25l  // Read the number of good/bad packets82,1944%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_GOOD_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INNST_OFFSET, &good_pkts);83,1945%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_ERR_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INNST_OFFSET, &bad_pkts);84,1946%[?12l[?25h[?25l  printw(" Good: %d Bad: %d", good_pkts, bad_pkts);85,1947%[?12l[?25h[?25l 86,0-148%[?12l[?25h[?25l  printw("\n");87,1748%[?12l[?25h[?25l 88,0-149%[?12l[?25h[?25l  // Verify if we should reset the counters89,1950%[?12l[?25h[?25l  /*if ((port_status & 0x1100) == 0x1100) {90,1951%[?12l[?25h[?25l  // Only reset if the number of good packets has incremented but the bad91,1951%[?12l[?25h[?25l  // packets have remained the same92,1952%[?12l[?25h[?25l if (bad_pkts == prev_bad_pkts[i] && good_pkts != prev_good_pkts[i]) { writeReg(&nf2, PHY_TEST_PHY_0_RX_CTRL_REG + i * PHY_TEST_PHY_GROUP_INST_@ 93,1953%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_PHY_0_RX_CTRL_REG + i * PHY_TEST_PHY_GROUP_INST__OFFSET, 0x3);94,1954%[?12l[?25h[?25l {  }95,754%[?12l[?25h[?25l {}96,0-155%[?12l[?25h[?25l  // Update the counters97,1956%[?12l[?25h[?25l  prev_bad_pkts[i] = bad_pkts;98,1956%[?12l[?25h[?25l  prev_good_pkts[i] = good_pkts;99,1957%[?12l[?25h[?25l  }*/100,758%[?12l[?25h[?25l 101,0-159%[?12l[?25h[?25l  // Update the good flag102,1959%[?12l[?25h[?25l if (bad_pkts != 0) good = 0;103,1961%[?12l[?25h[?25l4,15[?12l[?25h[?25l }105,362%[?12l[?25h[?25l6,0-1[?12l[?25h[?25l  // Print overall success/failure107,1962%[?12l[?25h[?25l  move(y, x);108,1363%[?12l[?25h[?25l  printw("PHY test: %s", good ? "pass" : "fail");109,1964%[?12l[?25h[?25l  move(y + 1 + NUM_PORTS, x);110,1965%[?12l[?25h[?25l 111,0-165%[?12l[?25h[?25l  return good;112,1466%[?12l[?25h[?25l } // phyShowStatusContinuous113,1967%[?12l[?25h[?25l 114,0-168%[?12l[?25h[?25l /*115,268%[?12l[?25h[?25l * Stop the interface */116,1970%[?12l[?25h[?25l7,3 [?12l[?25h[?25l void phyStopContinuous(void) {118,1970%[?12l[?25h[?25l  // Stop the test (and wait for the test to stop)119,1971%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_CTRL_REG, 0x00000000);120,1972%[?12l[?25h[?25l } // phyStopContinuous121,1973%[?12l[?25h[?25l 122,0-173%[?12l[?25h[?25l /*123,274%[?12l[?25h[?25l  * Get the result of the test124,1975%[?12l[?25h[?25l  *125,276%[?12l[?25h[?25l  * Return -- boolean indicating success126,1976%[?12l[?25h[?25l  */127,377%[?12l[?25h[?25l int phyGetResult(void) {128,1978%[?12l[?25h[?25l  unsigned int val;129,1979%[?12l[?25h[?25l  unsigned int port_status;130,1979%[?12l[?25h[?25l  unsigned int good_pkts;131,1980%[?12l[?25h[?25l  unsigned int bad_pkts;132,1981%[?12l[?25h[?25l 133,0-182%[?12l[?25h[?25l  int i;134,882%[?12l[?25h[?25l 135,0-183%[?12l[?25h[?25l  int good = 1;136,1584%[?12l[?25h[?25l 137,0-185%[?12l[?25h[?25l  // Read the individual port registers138,1985%[?12l[?25h[?25l  for (i = 0; i < NUM_PORTS; i++) {139,1986%[?12l[?25h[?25l  // Start with the status register140,1987%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_STATUS_REG + i * PHY_TEST_PHY_GROUP_INST_OFFFSET, &port_status);141,1988%[?12l[?25h[?25l  if ((port_status & 0x100) == 0) {142,1988%[?12l[?25h[?25l  good = 0;143,1589%[?12l[?25h[?25l { }144,590%[?12l[?25h[?25l {}145,0-191%[?12l[?25h[?25l  // Read the number of good/bad packets146,1991%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_GOOD_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INNST_OFFSET, &good_pkts);147,1992%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_ERR_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INSST_OFFSET, &bad_pkts);148,1993%[?12l[?25h[?25l 149,0-194%[?12l[?25h[?25l  // Update the good flag150,1994%[?12l[?25h[?25l  if (bad_pkts != 0) {151,1995%[?12l[?25h[?25l  good = 0;152,1596%[?12l[?25h[?25l { }153,597%[?12l[?25h[?25l {{} }154,397%[?12l[?25h[?25l {}155,0-198%[?12l[?25h[?25l  return good;156,1499%[?12l[?25h[?25l } // phyGetResult157,17Bot[?12l[?25h[?25l6,14[?12l[?25h[?25l5,0-1[?12l[?25h[?25l{}4,3 [?12l[?25h[?25l{{} }3,5[?12l[?25h[?25l{}2,15[?12l[?25h[?25l:[?12l[?25he[?25l[?12l[?25h[?25l [?12l[?25hs[?25l[?12l[?25he[?25l[?12l[?25hl[?25l[?12l[?25hf[?25l[?12l[?25ht[?25l[?12l[?25he[?25l[?12l[?25hs[?25l[?12l[?25ht[?25l[?12l[?25h.[?25l[?12l[?25hc[?25l[?12l[?25h [?25l"selftest.c" 512L, 10370C/* **************************************************************************** * vim:set shiftwidth=2 softtabstop=2 expandtab: * $Id: selftest.c 6010 2010-03-14 08:24:50Z grg $ * * Module: selftest.c * Project: NetFPGA 2.1 * Description: Interface with the self-test modules on the NetFPGA * to help diagnose problems. * * Change history: * */#include #include  #include #include  #include  #include  #include #include 1,1Top[?12l[?25h[?25l/\search hit BOTTOM, continuing at TOP E486: Pattern not found: \1,1Top[?12l[?25h[?25l/[?12l[?25hP[?25l[?12l[?25hH[?25l[?12l[?25hY[?25l[?12l[?25h [?25l regStopContinuous, regGetResult, }, { "MDIO interface", mdioResetContinuous, mdioShowStatusContinuous, mdioStopContinuous, mdioGetResult, }, { "PHY interface", phyResetContinuous, phyShowStatusContinuous, phyStopContinuous, phyGetResult, }, { "DRAM controller", dramResetContinuous, dramShowStatusContinuous, dramStopContinuous, dramGetResult,110,620%[?12l[?25h[?25l1[?12l[?25h[?25l5[?12l[?25h[?25l2[?12l[?25h[?25l3[?12l[?25h[?25l4[?12l[?25h[?25l5,4[?12l[?25h[?25l6,3[?12l[?25h[?25l7,5[?12l[?25h[?25l8[?12l[?25h[?25l9[?12l[?25h[?25l20[?12l[?25h[?25l1[?12l[?25h[?25l  },122,420%[?12l[?25h[?25l  {123,320%[?12l[?25h[?25l  "SRAM controller",124,520%[?12l[?25h[?25l  sramResetContinuous,125,520%[?12l[?25h[?25l  sramShowStatusContinuous,126,521%[?12l[?25h[?25l  sramStopContinuous,127,521%[?12l[?25h[?25l  sramGetResult,128,521%[?12l[?25h[?25l  },129,421%[?12l[?25h[?25l  {130,321%[?12l[?25h[?25l  "SATA controller",131,522%[?12l[?25h[?25l  serialResetContinuous,132,522%[?12l[?25h[?25l  serialShowStatusContinuous,133,522%[?12l[?25h[?25l  serialStopContinuous,134,522%[?12l[?25h[?25l  serialGetResult,135,522%[?12l[?25h[?25l  },136,423%[?12l[?25h[?25l  {137,323%[?12l[?25h[?25l  "DMA interface",138,523%[?12l[?25h[?25l  dmaResetContinuous,139,523%[?12l[?25h[?25l  dmaShowStatusContinuous,140,523%[?12l[?25h[?25l  dmaStopContinuous,141,524%[?12l[?25h[?25l  dmaGetResult,142,524%[?12l[?25h[?25l  },143,424%[?12l[?25h[?25l };144,224%[?12l[?25h[?25l 145,0-124%[?12l[?25h[?25l 146,0-125%[?12l[?25h[?25l /*147,225%[?12l[?25h[?25l  * Main function148,525%[?12l[?25h[?25l  */149,325%[?12l[?25h[?25l int main(int argc, char *argv[])150,525%[?12l[?25h[?25l {151,126%[?12l[?25h[?25l  // Set the default device152,526%[?12l[?25h[?25l  nf2.device_name = DEFAULT_IFACE;153,526%[?12l[?25h[?25l 154,0-126%[?12l[?25h[?25l  // Process the command line arguments155,526%[?12l[?25h[?25l  processArgs(argc, argv);156,527%[?12l[?25h[?25l 157,0-127%[?12l[?25h[?25l  // Check that the interface is valid and open it if possible158,527%[?12l[?25h[?25l  if (check_iface(&nf2))159,527%[?12l[?25h[?25l  {160,328%[?12l[?25h[?25l  exit(1);161,528%[?12l[?25h[?25l { }162,328%[?12l[?25h[?25l { } if (openDescriptor(&nf2))163,528%[?12l[?25h[?25l  {164,328%[?12l[?25h[?25l  exit(1);165,529%[?12l[?25h[?25l { }166,329%[?12l[?25h[?25l { }167,0-129%[?12l[?25h[?25l  // Verify that the correct device is downloaded168,529%[?12l[?25h[?25l  if (!checkVirtexBitfile(&nf2, DEVICE_PROJ_DIR,169,529%[?12l[?25h[?25l  DEVICE_MAJOR, DEVICE_MINOR, VERSION_ANY,170,1-830%[?12l[?25h[?25l  DEVICE_MAJOR, DEVICE_MINOR, VERSION_ANY)) {171,1-830%[?12l[?25h[?25l  fprintf(stderr, "%s\n", getVirtexBitfileErr());172,530%[?12l[?25h[?25l  exit(1);173,530%[?12l[?25h[?25l { }174,330%[?12l[?25h[?25l {} else {175,531%[?12l[?25h[?25l  printf(getDeviceInfoStr(&nf2));176,531%[?12l[?25h[?25l { }177,331%[?12l[?25h[?25l { }178,0-131%[?12l[?25h[?25l  // Add a signal handler179,531%[?12l[?25h[?25l  signal(SIGINT, sigint_handler);180,532%[?12l[?25h[?25l 181,0-132%[?12l[?25h[?25l  // Measure the clock rates182,532%[?12l[?25h[?25l  measureClocks();183,532%[?12l[?25h[?25l 184,0-132%[?12l[?25h[?25l  // Run the appropriate test185,533%[?12l[?25h[?25l  if (continuous) {186,533%[?12l[?25h[?25l  mainContinuous();187,533%[?12l[?25h[?25l { }188,333%[?12l[?25h[?25l { } else if (shortrun) {189,533%[?12l[?25h[?25l  mainOneShot();190,534%[?12l[?25h[?25l { }191,334%[?12l[?25h[?25l { }192,0-134%[?12l[?25h[?25l  // Close the network descriptor193,534%[?12l[?25h[?25l  closeDescriptor(&nf2);194,534%[?12l[?25h[?25l 195,0-135%[?12l[?25h[?25l  return 0;196,535%[?12l[?25h[?25l }197,135%[?12l[?25h[?25l 198,0-135%[?12l[?25h[?25l /*199,235%[?12l[?25h[?25l  * "Main" function for continuous mode200,536%[?12l[?25h[?25l  */201,336%[?12l[?25h[?25l void mainContinuous(void)202,536%[?12l[?25h[?25l {203,136%[?12l[?25h[?25l  // Set up curses204,537%[?12l[?25h[?25l  w = initscr();205,537%[?12l[?25h[?25l  cbreak();206,537%[?12l[?25h[?25l  halfdelay(1);207,537%[?12l[?25h[?25l  noecho();208,537%[?12l[?25h[?25l 209,0-138%[?12l[?25h[?25l  //init_work(); //initialization. one time effort210,538%[?12l[?25h[?25l 211,0-138%[?12l[?25h[?25l  // Run the test in continuous mode212,538%[?12l[?25h[?25l  run_continuous();213,538%[?12l[?25h[?25l  stop_continuous();214,539%[?12l[?25h[?25l 215,0-139%[?12l[?25h[?25l  // End the curses216,539%[?12l[?25h[?25l  endwin();217,539%[?12l[?25h[?25l {}218,139%[?12l[?25h[?25l {}219,0-140%[?12l[?25h[?25l /*220,240%[?12l[?25h[?25l  * "Main" function for one-shot mode221,540%[?12l[?25h[?25l  */222,340%[?12l[?25h[?25l void mainOneShot(void)223,540%[?12l[?25h[?25l {224,141%[?12l[?25h[?25l  int i;225,541%[?12l[?25h[?25l  int failed = 0;226,541%[?12l[?25h[?25l 227,0-141%[?12l[?25h[?25l  // Reset the board and initialize the tests228,541%[?12l[?25h[?25l  reset_board();229,542%[?12l[?25h[?25l  reset_continuous();230,542%[?12l[?25h[?25l 231,0-142%[?12l[?25h[?25l  // Run the test in one-shot mode mode232,542%[?12l[?25h[?25l  printf("NetFPGA selftest %s\n", SELFTEST_VERSION);233,542%[?12l[?25h[?25l  printf("Running");234,543%[?12l[?25h[?25l  fflush(stdout);235,543%[?12l[?25h[?25l  for (i = 0; i < ONE_SHOT_ITER; i++) {236,543%[?12l[?25h[?25l  sleep(1);237,543%[?12l[?25h[?25l  printf(".");238,543%[?12l[?25h[?25l  fflush(stdout);239,544%[?12l[?25h[?25l { }240,344%[?12l[?25h[?25l {} printf(" ");241,544%[?12l[?25h[?25l 242,0-144%[?12l[?25h[?25l  // Verify the results243,544%[?12l[?25h[?25l  for (i = 0; i < NUM_TESTS; i++) {244,545%[?12l[?25h[?25l  if (!modules[i].get_result()) {245,545%[?12l[?25h[?25l  if (!failed)246,545%[?12l[?25h[?25l  printf("FAILED. Failing tests: ");247,545%[?12l[?25h[?25l  else248,546%[?12l[?25h[?25l  printf(", ");249,546%[?12l[?25h[?25l  printf(modules[i].name);250,546%[?12l[?25h[?25l49[?12l[?25h[?25l8[?12l[?25h[?25l7[?12l[?25h[?25l6[?12l[?25h[?25l5[?12l[?25h[?25l4[?12l[?25h[?25l3[?12l[?25h[?25l2,0-1[?12l[?25h[?25l1,5 [?12l[?25h[?25l{}0,3[?12l[?25h[?25l{}39,5[?12l[?25h[?25l8[?12l[?25h[?25l7[?12l[?25h[?25l6[?12l[?25h[?25l5[?12l[?25h[?25l4[?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l1,0-1[?12l[?25h[?25l0,5 [?12l[?25h[?25l29[?12l[?25h[?25l8[?12l[?25h[?25l227,0-146%[?12l[?25h[?25l int failed = 0;226,546%[?12l[?25h[?25l int i;225,545%[?12l[?25h[?25l{224,145%[?12l[?25h[?25lvoid mainOneShot(void)223,545%[?12l[?25h[?25l */222,345%[?12l[?25h[?25l * "Main" function for one-shot mode221,544%[?12l[?25h[?25l/*220,244%[?12l[?25h[?25l219,0-144%[?12l[?25h[?25l}218,144%[?12l[?25h[?25l endwin();217,544%[?12l[?25h[?25l // End the curses216,543%[?12l[?25h[?25l7[?12l[?25h[?25l8,1[?12l[?25h[?25l9,0-1[?12l[?25h[?25l20,2 [?12l[?25h[?25l1,5[?12l[?25h[?25l2,3[?12l[?25h[?25l3,5[?12l[?25h[?25l4,1[?12l[?25h[?25l5,5[?12l[?25h[?25l6[?12l[?25h[?25l7,0-1[?12l[?25h[?25l8,5 [?12l[?25h[?25l9[?12l[?25h[?25l30[?12l[?25h[?25l1,0-1[?12l[?25h[?25l2,5 [?12l[?25h[?25l3[?12l[?25h[?25l4[?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l  fflush(stdout);239,544%[?12l[?25h[?25l { }240,344%[?12l[?25h[?25l {} printf(" ");241,544%[?12l[?25h[?25l 242,0-144%[?12l[?25h[?25l  // Verify the results243,544%[?12l[?25h[?25l  for (i = 0; i < NUM_TESTS; i++) {244,545%[?12l[?25h[?25l  if (!modules[i].get_result()) {245,545%[?12l[?25h[?25l  if (!failed)246,545%[?12l[?25h[?25l  printf("FAILED. Failing tests: ");247,545%[?12l[?25h[?25l  else248,546%[?12l[?25h[?25l  printf(", ");249,546%[?12l[?25h[?25l  printf(modules[i].name);250,546%[?12l[?25h[?25l 251,0-146%[?12l[?25h[?25l  // Record that the tests have failed252,546%[?12l[?25h[?25l  failed = 1;253,547%[?12l[?25h[?25l { }254,547%[?12l[?25h[?25l {{} }255,347%[?12l[?25h[?25l {}256,0-147%[?12l[?25h[?25l  // Terminat the tests257,547%[?12l[?25h[?25l  stop_continuous();258,548%[?12l[?25h[?25l 259,0-148%[?12l[?25h[?25l  // Check if the tests failed260,548%[?12l[?25h[?25l  if (!failed)261,548%[?12l[?25h[?25l  printf("PASSED\n");262,548%[?12l[?25h[?25l  else263,549%[?12l[?25h[?25l  printf("\n");264,549%[?12l[?25h[?25l }265,149%[?12l[?25h[?25l 266,0-149%[?12l[?25h[?25l /*267,249%[?12l[?25h[?25l  * Display a title bar268,550%[?12l[?25h[?25l  */269,350%[?12l[?25h[?25l void title_bar(void) {270,550%[?12l[?25h[?25l69,3[?12l[?25h[?25l8,5[?12l[?25h[?25l7,2[?12l[?25h[?25l6,0-1[?12l[?25h[?25l5,1 [?12l[?25h[?25l4,5[?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l1[?12l[?25h[?25l0[?12l[?25h[?25l59,0-1[?12l[?25h[?25l8,5 [?12l[?25h[?25l7[?12l[?25h[?25l6,0-1[?12l[?25h[?25l5,3 [?12l[?25h[?25l4,5[?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l1,0-1[?12l[?25h[?25l0,5 [?12l[?25h[?25l49[?12l[?25h[?25l8[?12l[?25h[?25l printf("FAILED. Failing tests: ");247,550%[?12l[?25h[?25l if (!failed)246,550%[?12l[?25h[?25l if (!modules[i].get_result()) {245,549%[?12l[?25h[?25l for (i = 0; i < NUM_TESTS; i++) {244,549%[?12l[?25h[?25l // Verify the results243,549%[?12l[?25h[?25l242,0-149%[?12l[?25h[?25l printf(" ");241,549%[?12l[?25h[?25l }240,348%[?12l[?25h[?25l fflush(stdout);239,548%[?12l[?25h[?25l printf(".");238,548%[?12l[?25h[?25l sleep(1);237,548%[?12l[?25h[?25l for (i = 0; i < ONE_SHOT_ITER; i++) {236,548%[?12l[?25h[?25l fflush(stdout);235,547%[?12l[?25h[?25l printf("Running");234,547%[?12l[?25h[?25l printf("NetFPGA selftest %s\n", SELFTEST_VERSION);233,547%[?12l[?25h[?25l // Run the test in one-shot mode mode232,547%[?12l[?25h[?25l231,0-147%[?12l[?25h[?25l reset_continuous();230,546%[?12l[?25h[?25l reset_board();229,546%[?12l[?25h[?25l // Reset the board and initialize the tests228,546%[?12l[?25h[?25l227,0-146%[?12l[?25h[?25l int failed = 0;226,546%[?12l[?25h[?25l int i;225,545%[?12l[?25h[?25l{224,145%[?12l[?25h[?25lvoid mainOneShot(void)223,545%[?12l[?25h[?25l */222,345%[?12l[?25h[?25l * "Main" function for one-shot mode221,544%[?12l[?25h[?25l/*220,244%[?12l[?25h[?25l219,0-144%[?12l[?25h[?25l}218,144%[?12l[?25h[?25l endwin();217,544%[?12l[?25h[?25l // End the curses216,543%[?12l[?25h[?25l215,0-143%[?12l[?25h[?25l stop_continuous();214,543%[?12l[?25h[?25l run_continuous();213,543%[?12l[?25h[?25l // Run the test in continuous mode212,543%[?12l[?25h[?25l211,0-142%[?12l[?25h[?25l //init_work(); //initialization. one time effort210,542%[?12l[?25h[?25l209,0-142%[?12l[?25h[?25l noecho();208,542%[?12l[?25h[?25l halfdelay(1);207,542%[?12l[?25h[?25l cbreak();206,541%[?12l[?25h[?25l w = initscr();205,541%[?12l[?25h[?25l // Set up curses204,541%[?12l[?25h[?25l{}203,141%[?12l[?25h[?25lvoid mainContinuous(void) {}202,541%[?12l[?25h[?25l */201,340%[?12l[?25h[?25l * "Main" function for continuous mode200,540%[?12l[?25h[?25l/*199,240%[?12l[?25h[?25l198,0-140%[?12l[?25h[?25l}197,140%[?12l[?25h[?25l return 0;196,539%[?12l[?25h[?25l195,0-139%[?12l[?25h[?25l closeDescriptor(&nf2);194,539%[?12l[?25h[?25l // Close the network descriptor193,539%[?12l[?25h[?25l4[?12l[?25h[?25l5,0-1[?12l[?25h[?25l6,5 [?12l[?25h[?25l7,1[?12l[?25h[?25l8,0-1[?12l[?25h[?25l9,2 [?12l[?25h[?25l200,5[?12l[?25h[?25l1,3[?12l[?25h[?25l2,5[?12l[?25h[?25l3,1[?12l[?25h[?25l4,5[?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l9,0-1[?12l[?25h[?25l10,5 [?12l[?25h[?25l1,0-1[?12l[?25h[?25l2,5 [?12l[?25h[?25l3[?12l[?25h[?25l4[?12l[?25h[?25l5,0-1[?12l[?25h[?25l  // End the curses216,539%[?12l[?25h[?25l  endwin();217,539%[?12l[?25h[?25l {}218,139%[?12l[?25h[?25l {}219,0-140%[?12l[?25h[?25l /*220,240%[?12l[?25h[?25l  * "Main" function for one-shot mode221,540%[?12l[?25h[?25l  */222,340%[?12l[?25h[?25l void mainOneShot(void)223,540%[?12l[?25h[?25l {224,141%[?12l[?25h[?25l  int i;225,541%[?12l[?25h[?25l  int failed = 0;226,541%[?12l[?25h[?25l 227,0-141%[?12l[?25h[?25l  // Reset the board and initialize the tests228,541%[?12l[?25h[?25l  reset_board();229,542%[?12l[?25h[?25l  reset_continuous();230,542%[?12l[?25h[?25l 231,0-142%[?12l[?25h[?25l0,5 [?12l[?25h[?25l29[?12l[?25h[?25l3[?12l[?25h[?25l30[?12l[?25h[?25l /\ * Run the program in continuous mode */ void run_continuous(void) { int ch = ERR; int count; int prev_lines; int prev_cols; int i; // Reset the board and initialize the tests reset_board(); reset_continuous(); // Run the tests continuously and wait while (1) { // Remember the screen dimensions prev_lines = LINES; prev_cols = COLS; // Clear the screen and move to the top corner erase(); move(0,0);302,359%[?12l[?25h[?25l/\ if (continuous) stop_continuous(); printf("Caught SIGINT. Exiting...\n"); exit(0); } } /* * Invoke the reset functions for continuous mode */ void reset_continuous(void) { int i; for (i = 0; i < NUM_TESTS; i++) { modules[i].reset_continuous(); } } /* * Invoke the stop functions for continuous mode */ void stop_continuous(void) {383,675%[?12l[?25h[?25l4[?12l[?25h[?25l5,0-1[?12l[?25h[?25l6,6 [?12l[?25h[?25l7[?12l[?25h[?25l6[?12l[?25h[?25l5,0-1[?12l[?25h[?25l4,6 [?12l[?25h[?25l3[?12l[?25h[?25l2,3[?12l[?25h[?25l1,6[?12l[?25h[?25l0,2[?12l[?25h[?25l79,0-1[?12l[?25h[?25l8,1 [?12l[?25h[?25l7,3[?12l[?25h[?25l6,6[?12l[?25h[?25l5[?12l[?25h[?25l4,0-1[?12l[?25h[?25l3,6 [?12l[?25h[?25l2[?12l[?25h[?25l371,0-175%[?12l[?25h[?25l endwin();370,675%[?12l[?25h[?25l if (signum == SIGINT) {369,675%[?12l[?25h[?25lvoid sigint_handler(int signum) {()368,675%[?12l[?25h[?25l */367,374%[?12l[?25h[?25l * Handle SIGINT gracefully366,674%[?12l[?25h[?25l/*365,274%[?12l[?25h[?25l364,0-174%[?12l[?25h[?25l}363,174%[?12l[?25h[?25l writeReg(&nf2, CPCI_CTRL_REG, val | CPCI_CTRL_CNET_RESET);362,673%[?12l[?25h[?25l /* Write to the control register to reset it */361,673%[?12l[?25h[?25l360,0-173%[?12l[?25h[?25l readReg(&nf2, CPCI_CTRL_REG, &val);359,673%[?12l[?25h[?25l/\ */ void reset_continuous(void) {383,673%[?12l[?25h[?25l /\ int i; for (i = 0; i < NUM_TESTS; i++) { modules[i].reset_continuous();387,1674%[?12l[?25h[?25l /\search hit BOTTOM, continuing at TOP//void show_stats (int loop_iter); //bool show_status_serial_test(void); //bool show_status_sram_test(void); //bool show_status_dram_test(void); //bool show_status_mii_test(void); //bool show_status_phy_test(void); //bool show_status_reg_test(void); //void sram_sw_test(SW_TEST_EFFORT_LEVEL ); void processArgs (int, char **); void usage (char*); void run_continuous(void); void reset_continuous(void); void stop_continuous(void); void sigint_handler(int signum); void reset_board(void); void title_bar(void); void clear_line(void); #define NUM_TESTS 8 /* Selftest module interface */ struct test_module modules[NUM_TESTS] = { { "Clock select",78,613% search hit BOTTOM, continuing at TOP78,613%[?12l[?25h[?25l/\/* * "Main" function for one-shot mode */ void mainOneShot(void) { int i; int failed = 0; // Reset the board and initialize the tests reset_board(); reset_continuous(); // Run the test in one-shot mode mode printf("NetFPGA selftest %s\n", SELFTEST_VERSION); printf("Running"); fflush(stdout); for (i = 0; i < ONE_SHOT_ITER; i++) { sleep(1); printf("."); fflush(stdout); } printf(" ");230,344%[?12l[?25h[?25l1,0-1[?12l[?25h[?25l2,3 [?12l[?25h[?25l3[?12l[?25h[?25l4[?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l9[?12l[?25h[?25l{}40[?12l[?25h[?25l{}1[?12l[?25h[?25l 242,0-144%[?12l[?25h[?25l  // Verify the results243,344%[?12l[?25h[?25l2,0-1[?12l[?25h[?25l1,3 [?12l[?25h[?25l{}0[?12l[?25h[?25l{}39[?12l[?25h[?25l8[?12l[?25h[?25l7[?12l[?25h[?25l6[?12l[?25h[?25l4[?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l ()7[?12l[?25h[?25l()8[?12l[?25h[?25l9[?12l[?25h[?25l10[?12l[?25h[?25l1[?12l[?25h[?25l2[?12l[?25h[?25l3[?12l[?25h[?25l4[?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l9[?12l[?25h[?25l/\search hit BOTTOM, continuing at TOP#include "selftest_phy.h" #include "selftest_mdio.h" #include "selftest_reg.h" #include "selftest_clk.h" #include "selftest_dma.h" #define PATHLEN 80 #define DEFAULT_IFACE "nf2c0" #define SELFTEST_VERSION "1.00 alpha" #define ONE_SHOT_ITER 5 typedef enum {LOW = 0, HIGH = 1} SW_TEST_EFFORT_LEVEL; /* Global vars */ struct nf2device nf2; int verbose = 0; int continuous = 0; int shortrun = 1; int no_sata_flg = 0; FILE * log_file;48,97% search hit BOTTOM, continuing at TOP48,97%[?12l[?25h[?25l/\ int i; int failed = 0; // Reset the board and initialize the tests reset_board(); reset_continuous(); // Run the test in one-shot mode mode printf("NetFPGA selftest %s\n", SELFTEST_VERSION); printf("Running"); fflush(stdout); for (i = 0; i < ONE_SHOT_ITER; i++) { sleep(1); printf("."); fflush(stdout); } printf(" "); // Verify the results for (i = 0; i < NUM_TESTS; i++) { if (!modules[i].get_result()) { if (!failed) printf("FAILED. Failing tests: ");236,1945%[?12l[?25h[?25l7,13[?12l[?25h[?25l8,16[?12l[?25h[?25l9,19[?12l[?25h[?25l{}40,3 [?12l[?25h[?25l{}1,14[?12l[?25h[?25l2,0-1[?12l[?25h[?25l3,19 [?12l[?25h[?25l4[?12l[?25h[?25l[i]5[?12l[?25h[?25l[i]()6,18[?12l[?25h[?25l()7,19[?12l[?25h[?25l  else248,1046%[?12l[?25h[?25l  printf(", ");249,1946%[?12l[?25h[?25l  printf(modules[i].name);250,1946%[?12l[?25h[?25l 251,0-146%[?12l[?25h[?25l  // Record that the tests have failed252,1946%[?12l[?25h[?25l  failed = 1;253,1747%[?12l[?25h[?25l { }254,547%[?12l[?25h[?25l {{} }255,347%[?12l[?25h[?25l {}256,0-147%[?12l[?25h[?25l  // Terminat the tests257,1947%[?12l[?25h[?25l  stop_continuous();258,1948%[?12l[?25h[?25l ()259,0-148%[?12l[?25h[?25l  // Check if the tests failed260,1948%[?12l[?25h[?25l  if (!failed)261,1448%[?12l[?25h[?25l () printf("PASSED\n");262,1948%[?12l[?25h[?25l  else263,649%[?12l[?25h[?25l  printf("\n");264,1749%[?12l[?25h[?25l }265,149%[?12l[?25h[?25l 266,0-149%[?12l[?25h[?25l /*267,249%[?12l[?25h[?25l6,0-1[?12l[?25h[?25l5,1 [?12l[?25h[?25l4,17[?12l[?25h[?25l3,6 [?12l[?25h[?25l2,19[?12l[?25h[?25l()1,14[?12l[?25h[?25l()0,19[?12l[?25h[?25l59,0-1[?12l[?25h[?25l()8,19 [?12l[?25h[?25l()7[?12l[?25h[?25l6,0-1[?12l[?25h[?25l5,3 [?12l[?25h[?25l{}4,5[?12l[?25h[?25l{}3,17[?12l[?25h[?25l2,19[?12l[?25h[?25l1,0-1[?12l[?25h[?25l0,19 [?12l[?25h[?25l49[?12l[?25h[?25l8,10[?12l[?25h[?25l7,19[?12l[?25h[?25l()6,18[?12l[?25h[?25l[i]()5,19[?12l[?25h[?25l for (i = 0; i < NUM_TESTS; i++) {[i]244,1949%[?12l[?25h[?25l // Verify the results243,1949%[?12l[?25h[?25l242,0-149%[?12l[?25h[?25l printf(" ");241,1449%[?12l[?25h[?25l }240,348%[?12l[?25h[?25l fflush(stdout);239,1948%[?12l[?25h[?25l printf(".");238,1648%[?12l[?25h[?25l9,19[?12l[?25h[?25l40,3 [?12l[?25h[?25l1,14[?12l[?25h[?25l2,0-1[?12l[?25h[?25l3,19 [?12l[?25h[?25l4[?12l[?25h[?25l[i]5[?12l[?25h[?25l[i]()6,18[?12l[?25h[?25l()7,19[?12l[?25h[?25l8,10[?12l[?25h[?25l9,19[?12l[?25h[?25l50[?12l[?25h[?25l1,0-1[?12l[?25h[?25l2,19 [?12l[?25h[?25l3,17[?12l[?25h[?25l6[?12l[?25h[?25l5[?12l[?25h[?25l4[?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l1[?12l[?25h[?25l0[?12l[?25h[?25l9 [?12l[?25h[?25l8[?12l[?25h[?25l7[?12l[?25h[?25l{}4,5[?12l[?25h[?25l{}3,7[?12l[?25h[?25l2[?12l[?25h[?25l1,0-1[?12l[?25h[?25l0,7 [?12l[?25h[?25l49[?12l[?25h[?25l8[?12l[?25h[?25l7[?12l[?25h[?25l6[?12l[?25h[?25l5[?12l[?25h[?25l()4[?12l[?25h[?25l()3[?12l[?25h[?25l2,0-1[?12l[?25h[?25l1,7 [?12l[?25h[?25l0,3[?12l[?25h[?25l39,7[?12l[?25h[?25l8[?12l[?25h[?25l sleep(1);237,748%[?12l[?25h[?25l for (i = 0; i < ONE_SHOT_ITER; i++) {236,748%[?12l[?25h[?25l fflush(stdout);()235,747%[?12l[?25h[?25l printf("Running");234,747%[?12l[?25h[?25l printf("NetFPGA selftest %s\n", SELFTEST_VERSION);233,747%[?12l[?25h[?25l // Run the test in one-shot mode mode232,747%[?12l[?25h[?25l231,0-147%[?12l[?25h[?25l2,7 [?12l[?25h[?25l3[?12l[?25h[?25l4[?12l[?25h[?25l5[?12l[?25h[?25l()6[?12l[?25h[?25l()7[?12l[?25h[?25l8[?12l[?25h[?25l9[?12l[?25h[?25l{}40,3[?12l[?25h[?25l{}1,7[?12l[?25h[?25l2,0-1[?12l[?25h[?25l3,7 [?12l[?25h[?25l()4[?12l[?25h[?25l()5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l9[?12l[?25h[?25l50[?12l[?25h[?25l1,0-1[?12l[?25h[?25l2,7 [?12l[?25h[?25l3[?12l[?25h[?25l { }254,547%[?12l[?25h[?25l {{} }255,347%[?12l[?25h[?25l {}256,0-147%[?12l[?25h[?25l  // Terminat the tests257,747%[?12l[?25h[?25l:[?12l[?25h![?25l[?12l[?25hl[?25l[?12l[?25hs[?25l[?12l[?25h[?25l [?12l[?25h-[?25l[?12l[?25ha[?25l[?12l[?25hl[?25l[?12l[?25h [?25l[?1l>[?12l[?25h[?1049l total 352 drwxr-xr-x 2 netfpga netfpga 4096 2011-03-10 15:04 . drwxr-xr-x 8 netfpga netfpga 4096 2011-03-09 18:24 .. -rwxr-xr-x 1 netfpga netfpga 26966 2011-03-09 19:22 bad_pkt_dump -rw-r--r-- 1 netfpga netfpga 2386 2011-03-09 18:24 bad_pkt_dump.c -rw-r--r-- 1 netfpga netfpga 4296 2011-03-09 19:22 bad_pkt_dump.o -rw-r--r-- 1 netfpga netfpga 903 2011-03-09 18:24 Makefile -rw-r--r-- 1 netfpga netfpga 3212 2011-03-09 18:24 or_data_types.h -rw-r--r-- 1 netfpga netfpga 731 2011-03-09 18:24 or_ip.c -rw-r--r-- 1 netfpga netfpga 129 2011-03-09 18:24 or_ip.h -rw-r--r-- 1 netfpga netfpga 3464 2011-03-09 19:22 or_ip.o -rw-r--r-- 1 netfpga netfpga 872 2011-03-09 18:24 or_utils.c -rw-r--r-- 1 netfpga netfpga 292 2011-03-09 18:24 or_utils.h -rw-r--r-- 1 netfpga netfpga 4108 2011-03-09 19:22 or_utils.o -rwxr-xr-x 1 netfpga netfpga 67122 2011-03-09 19:22 selftest -rw-r--r-- 1 netfpga netfpga 10370 2011-03-09 18:24 selftest.c -rw-r--r-- 1 netfpga netfpga 3581 2011-03-09 18:24 selftest_clk.c -rw-r--r-- 1 netfpga netfpga 516 2011-03-09 18:24 selftest_clk.h -rw-r--r-- 1 netfpga netfpga 5740 2011-03-09 19:22 selftest_clk.o -rw-r--r-- 1 root root 16384 2011-03-10 15:05 .selftest.c.swp -rw-r--r-- 1 netfpga netfpga 6094 2011-03-09 18:24 selftest_dma.c -rw-r--r-- 1 netfpga netfpga 644 2011-03-09 18:24 selftest_dma.h -rw-r--r-- 1 netfpga netfpga 11516 2011-03-09 19:22 selftest_dma.o -rw-r--r-- 1 netfpga netfpga 2660 2011-03-09 18:24 selftest_dram.c -rw-r--r-- 1 netfpga netfpga 554 2011-03-09 18:24 selftest_dram.h -rw-r--r-- 1 netfpga netfpga 4844 2011-03-09 19:22 selftest_dram.o -rw-r--r-- 1 netfpga netfpga 859 2011-03-09 18:24 selftest.h -rw-r--r-- 1 netfpga netfpga 4628 2011-03-09 18:24 selftest_mdio.c -rw-r--r-- 1 netfpga netfpga 526 2011-03-09 18:24 selftest_mdio.h -rw-r--r-- 1 netfpga netfpga 7932 2011-03-09 19:22 selftest_mdio.o -rw-r--r-- 1 netfpga netfpga 17076 2011-03-09 19:22 selftest.o -rw-r--r-- 1 netfpga netfpga 3955 2011-03-09 18:24 selftest_phy.c -rw-r--r-- 1 netfpga netfpga 487 2011-03-09 18:24 selftest_phy.h -rw-r--r-- 1 netfpga netfpga 6612 2011-03-09 19:22 selftest_phy.o -rw-r--r-- 1 netfpga netfpga 1933 2011-03-09 18:24 selftest_reg.c -rw-r--r-- 1 netfpga netfpga 520 2011-03-09 18:24 selftest_reg.h -rw-r--r-- 1 netfpga netfpga 4100 2011-03-09 19:22 selftest_reg.o -rw-r--r-- 1 netfpga netfpga 5986 2011-03-09 18:24 selftest_serial.c -rw-r--r-- 1 netfpga netfpga 512 2011-03-09 18:24 selftest_serial.h -rw-r--r-- 1 netfpga netfpga 6608 2011-03-09 19:22 selftest_serial.o -rw-r--r-- 1 netfpga netfpga 3258 2011-03-09 18:24 selftest_sram.c -rw-r--r-- 1 netfpga netfpga 564 2011-03-09 18:24 selftest_sram.h -rw-r--r-- 1 netfpga netfpga 4976 2011-03-09 19:22 selftest_sram.o Press ENTER or type command to continue[?1049h[?1h=[?25l fflush(stdout); for (i = 0; i < ONE_SHOT_ITER; i++) { sleep(1); printf("."); fflush(stdout); } printf(" "); // Verify the results for (i = 0; i < NUM_TESTS; i++) { if (!modules[i].get_result()) { if (!failed) printf("FAILED. Failing tests: "); else printf(", "); printf(modules[i].name); // Record that the tests have failed failed = 1; } } // Terminat the tests257,747%[?12l[?25h[?25l6,0-1[?12l[?25h[?25l{}5,3 [?12l[?25h[?25l{{} }4,5[?12l[?25h[?25l{}3,7[?12l[?25h[?25l2[?12l[?25h[?25l1,0-1[?12l[?25h[?25l0,7 [?12l[?25h[?25l49[?12l[?25h[?25l8[?12l[?25h[?25l7[?12l[?25h[?25l6[?12l[?25h[?25l5[?12l[?25h[?25l()4[?12l[?25h[?25l()3[?12l[?25h[?25l2,0-1[?12l[?25h[?25l1,7 [?12l[?25h[?25l{}0,3[?12l[?25h[?25l{}39,7[?12l[?25h[?25l8[?12l[?25h[?25l7[?12l[?25h[?25l()6[?12l[?25h[?25l()5[?12l[?25h[?25l printf("Running");234,747%[?12l[?25h[?25l printf("NetFPGA selftest %s\n", SELFTEST_VERSION);233,747%[?12l[?25h[?25l // Run the test in one-shot mode mode232,747%[?12l[?25h[?25l3[?12l[?25h[?25l4[?12l[?25h[?25l5[?12l[?25h[?25l()6[?12l[?25h[?25l()7[?12l[?25h[?25l8[?12l[?25h[?25l9[?12l[?25h[?25l{}40,3[?12l[?25h[?25l{}1,7[?12l[?25h[?25l2,0-1[?12l[?25h[?25l3,7 [?12l[?25h[?25l()4[?12l[?25h[?25l()5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l9[?12l[?25h[?25l50[?12l[?25h[?25l1,0-1[?12l[?25h[?25l2,7 [?12l[?25h[?25l3[?12l[?25h[?25l{}4,5[?12l[?25h[?25l {{} }255,347%[?12l[?25h[?25l {}256,0-147%[?12l[?25h[?25l{}5,3 [?12l[?25h[?25l{{} }4,5[?12l[?25h[?25l{}3,7[?12l[?25h[?25l2[?12l[?25h[?25l1,0-1[?12l[?25h[?25l0,7 [?12l[?25h[?25l49[?12l[?25h[?25l8[?12l[?25h[?25l7[?12l[?25h[?25l6[?12l[?25h[?25l5[?12l[?25h[?25l()4[?12l[?25h[?25l()3[?12l[?25h[?25l2,0-1[?12l[?25h[?25l1,7 [?12l[?25h[?25l{}0,3[?12l[?25h[?25l{}39,7[?12l[?25h[?25l8[?12l[?25h[?25l7[?12l[?25h[?25l()6[?12l[?25h[?25l()5[?12l[?25h[?25l4[?12l[?25h[?25l printf("NetFPGA selftest %s\n", SELFTEST_VERSION);233,747%[?12l[?25h[?25l // Run the test in one-shot mode mode232,747%[?12l[?25h[?25l231,0-147%[?12l[?25h[?25l reset_continuous();230,746%[?12l[?25h[?25l reset_board();229,746%[?12l[?25h[?25l // Reset the board and initialize the tests228,746%[?12l[?25h[?25l227,0-146%[?12l[?25h[?25l int failed = 0;226,746%[?12l[?25h[?25l int i;225,745%[?12l[?25h[?25l{224,145%[?12l[?25h[?25lvoid mainOneShot(void)223,745%[?12l[?25h[?25l */222,345%[?12l[?25h[?25l * "Main" function for one-shot mode221,744%[?12l[?25h[?25l2,3[?12l[?25h[?25l3,7[?12l[?25h[?25l4,1[?12l[?25h[?25l5,7[?12l[?25h[?25l6[?12l[?25h[?25l7,0-1[?12l[?25h[?25l8,7 [?12l[?25h[?25l9[?12l[?25h[?25l6[?12l[?25h[?25l5[?12l[?25h[?25l30[?12l[?25h[?25l4[?12l[?25h[?25l3[?12l[?25h[?25l/\ * Run the program in continuous mode */ void run_continuous(void) { int ch = ERR; int count; int prev_lines; int prev_cols; int i; // Reset the board and initialize the tests reset_board(); reset_continuous(); // Run the tests continuously and wait while (1) { // Remember the screen dimensions prev_lines = LINES; prev_cols = COLS; // Clear the screen and move to the top corner erase(); move(0,0);302,359%[?12l[?25h[?25l/\ if (continuous) stop_continuous(); printf("Caught SIGINT. Exiting...\n"); exit(0); } } /* * Invoke the reset functions for continuous mode */ void reset_continuous(void) { int i; for (i = 0; i < NUM_TESTS; i++) { modules[i].reset_continuous(); } } /* * Invoke the stop functions for continuous mode */ void stop_continuous(void) {383,675%[?12l[?25h[?25l:[?12l[?25he[?25l[?12l[?25h[?25l [?12l[?25h#[?25l[?12l[?25h [?25l"selftest_phy.c" 157L, 3955C // Read the individual port registers for (i = 0; i < NUM_PORTS; i++) { // Start with the status register readReg(&nf2, PHY_TEST_PHY_0_RX_STATUS_REG + i * PHY_TEST_PHY_GROUP_INST_OFFFSET, &port_status); if ((port_status & 0x100) == 0) { good = 0; } // Read the number of good/bad packets readReg(&nf2, PHY_TEST_PHY_0_RX_GOOD_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INNST_OFFSET, &good_pkts); readReg(&nf2, PHY_TEST_PHY_0_RX_ERR_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INSST_OFFSET, &bad_pkts); // Update the good flag if (bad_pkts != 0) { good = 0; } } return good; } // phyGetResult152,7Bot[?12l[?25h[?25l/[?12l[?25hr[?25l[?12l[?25he[?25l[?12l[?25hs[?25l[?12l[?25he[?25l[?12l[?25ht[?25l[?12l[?25h_[?25l[?12l[?25hc[?25l[?12l[?25ho[?25l[?12l[?25hn[?25l[?12l[?25h [?25lsearch hit BOTTOM, continuing at TOP E486: Pattern not found: reset_con152,7Bot[?12l[?25h[?25l:[?12l[?25h1[?25l[?12l[?25h [?25l/* **************************************************************************** * vim:set shiftwidth=2 softtabstop=2 expandtab: * $Id: selftest_phy.c 5971 2010-03-06 06:44:56Z grg $ * * Module: selftest_phy.c * Project: NetFPGA selftest * Description: SATA selftest module * * Change history: * */ #include "../lib/C/reg_defines_selftest.h" #include "selftest.h" #include "selftest_phy.h" #include  #include  #define NUM_PORTS 4 static int prev_good_pkts[NUM_PORTS]; static int prev_bad_pkts[NUM_PORTS];1,1Top[?12l[?25h[?25l2[?12l[?25h[?25l3[?12l[?25h[?25l4[?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l9[?12l[?25h[?25l10,1[?12l[?25h[?25l1[?12l[?25h[?25l2,0-1[?12l[?25h[?25l3,1 [?12l[?25h[?25l4[?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8,0-1[?12l[?25h[?25l9,1 [?12l[?25h[?25l20,0-1[?12l[?25h[?25l1,1 [?12l[?25h[?25l2[?12l[?25h[?25l3,0-1[?12l[?25h[?25l /*24,10%[?12l[?25h[?25l  * Reset the interface and configure it for continuous operation25,11%[?12l[?25h[?25l  */26,12%[?12l[?25h[?25l void phyResetContinuous(void) {27,12%[?12l[?25h[?25l  int i;28,13%[?12l[?25h[?25l 29,0-14%[?12l[?25h[?25l  for (i = 0; i < NUM_PORTS; i++) {30,15%[?12l[?25h[?25l  prev_good_pkts[i] = 0;31,15%[?12l[?25h[?25l  prev_bad_pkts[i] = 0;32,16%[?12l[?25h[?25l  }33,17%[?12l[?25h[?25l 34,0-18%[?12l[?25h[?25l  // Stop the test (and wait for the test to stop)35,18%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_CTRL_REG, 0x0);36,19%[?12l[?25h[?25l  sleep(1);37,110%[?12l[?25h[?25l 38,0-111%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_PATTERN_REG, PHY_TEST_PATTERN_ENABLE_MASK);39,111%[?12l[?25h[?25l 40,0-112%[?12l[?25h[?25l  // Start the test41,113%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_CTRL_REG, PHY_TEST_CTRL_REPEAT);42,114%[?12l[?25h[?25l {} // phyResetContinuous43,114%[?12l[?25h[?25l {}44,0-115%[?12l[?25h[?25l /*45,116%[?12l[?25h[?25l  * Show the status of the SATA test when running in continuous mode46,117%[?12l[?25h[?25l  *47,117%[?12l[?25h[?25l  * Return -- boolean indicating success48,118%[?12l[?25h[?25l  */49,119%[?12l[?25h[?25l int phyShowStatusContinuous(void) {50,120%[?12l[?25h[?25l  unsigned int val;51,120%[?12l[?25h[?25l  unsigned int port_status;52,121%[?12l[?25h[?25l  unsigned int good_pkts;53,122%[?12l[?25h[?25l  unsigned int bad_pkts;54,123%[?12l[?25h[?25l 55,0-123%[?12l[?25h[?25l  int i;56,124%[?12l[?25h[?25l 57,0-125%[?12l[?25h[?25l  int x, y;58,126%[?12l[?25h[?25l 59,0-126%[?12l[?25h[?25l  int good = 1;60,127%[?12l[?25h[?25l 61,0-128%[?12l[?25h[?25l  // Store the current screen position62,129%[?12l[?25h[?25l  getyx(stdscr, y, x);63,129%[?12l[?25h[?25l2[?12l[?25h[?25l1,0-1[?12l[?25h[?25l0,1 [?12l[?25h[?25l59,0-1[?12l[?25h[?25l8,1 [?12l[?25h[?25l7,0-1[?12l[?25h[?25l6,1 [?12l[?25h[?25l5,0-1[?12l[?25h[?25l4,1 [?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l1[?12l[?25h[?25l0[?12l[?25h[?25l49[?12l[?25h[?25l8[?12l[?25h[?25l7[?12l[?25h[?25l6[?12l[?25h[?25l5[?12l[?25h[?25l4,0-1[?12l[?25h[?25l3,1 [?12l[?25h[?25l2[?12l[?25h[?25l1[?12l[?25h[?25l40,0-129%[?12l[?25h[?25l writeReg(&nf2, PHY_TEST_PATTERN_REG, PHY_TEST_PATTERN_ENABLE_MASK);39,128%[?12l[?25h[?25l38,0-127%[?12l[?25h[?25l sleep(1);37,126%[?12l[?25h[?25l writeReg(&nf2, PHY_TEST_CTRL_REG, 0x0);36,126%[?12l[?25h[?25l // Stop the test (and wait for the test to stop)35,125%[?12l[?25h[?25l34,0-124%[?12l[?25h[?25l5,1 [?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8,0-1[?12l[?25h[?25l9,1 [?12l[?25h[?25l40,0-1[?12l[?25h[?25l1,1 [?12l[?25h[?25l2[?12l[?25h[?25l3[?12l[?25h[?25l4,0-1[?12l[?25h[?25l5,1 [?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l9[?12l[?25h[?25l50[?12l[?25h[?25l1[?12l[?25h[?25l2[?12l[?25h[?25l3[?12l[?25h[?25l4[?12l[?25h[?25l5,0-1[?12l[?25h[?25l6,1 [?12l[?25h[?25l 57,0-125%[?12l[?25h[?25l  int x, y;58,126%[?12l[?25h[?25l 59,0-126%[?12l[?25h[?25l  int good = 1;60,127%[?12l[?25h[?25l 61,0-128%[?12l[?25h[?25l  // Store the current screen position62,129%[?12l[?25h[?25l  getyx(stdscr, y, x);63,129%[?12l[?25h[?25l 64,0-130%[?12l[?25h[?25l  // Move down a line65,131%[?12l[?25h[?25l  move(y + 1, x);66,132%[?12l[?25h[?25l 67,0-132%[?12l[?25h[?25l  // Read the individual port registers68,133%[?12l[?25h[?25l  for (i = 0; i < NUM_PORTS; i++) {69,134%[?12l[?25h[?25l  printw(" Port %d:", i + 1);70,135%[?12l[?25h[?25l 71,0-135%[?12l[?25h[?25l  // Start with the status register72,136%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_STATUS_REG + i * PHY_TEST_PHY_GROUP_INST_OFFFSET, &port_status);73,137%[?12l[?25h[?25l  if (port_status & 0x100) {74,138%[?12l[?25h[?25l  printw(" link w/ %d", (port_status & 0xf0000) >> 16);75,139%[?12l[?25h[?25l  }76,140%[?12l[?25h[?25l  else {77,140%[?12l[?25h[?25l  printw(" no link");78,141%[?12l[?25h[?25l  good = 0;79,142%[?12l[?25h[?25l  }80,142%[?12l[?25h[?25l 81,0-143%[?12l[?25h[?25l  // Read the number of good/bad packets82,144%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_GOOD_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INNST_OFFSET, &good_pkts);83,145%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_ERR_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INNST_OFFSET, &bad_pkts);84,146%[?12l[?25h[?25l  printw(" Good: %d Bad: %d", good_pkts, bad_pkts);85,147%[?12l[?25h[?25l 86,0-148%[?12l[?25h[?25l  printw("\n");87,148%[?12l[?25h[?25l 88,0-149%[?12l[?25h[?25l  // Verify if we should reset the counters89,150%[?12l[?25h[?25l  /*if ((port_status & 0x1100) == 0x1100) {90,151%[?12l[?25h[?25l  // Only reset if the number of good packets has incremented but the bad91,151%[?12l[?25h[?25l  // packets have remained the same92,152%[?12l[?25h[?25l if (bad_pkts == prev_bad_pkts[i] && good_pkts != prev_good_pkts[i]) { writeReg(&nf2, PHY_TEST_PHY_0_RX_CTRL_REG + i * PHY_TEST_PHY_GROUP_INST_@ 93,153%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_PHY_0_RX_CTRL_REG + i * PHY_TEST_PHY_GROUP_INST__OFFSET, 0x3);94,154%[?12l[?25h[?25l  }95,154%[?12l[?25h[?25l 96,0-155%[?12l[?25h[?25l  // Update the counters97,156%[?12l[?25h[?25l  prev_bad_pkts[i] = bad_pkts;98,156%[?12l[?25h[?25l  prev_good_pkts[i] = good_pkts;99,157%[?12l[?25h[?25l  }*/100,158%[?12l[?25h[?25l 101,0-159%[?12l[?25h[?25l  // Update the good flag102,159%[?12l[?25h[?25l if (bad_pkts != 0) good = 0;103,161%[?12l[?25h[?25l4[?12l[?25h[?25l }105,162%[?12l[?25h[?25l6,0-1[?12l[?25h[?25l  // Print overall success/failure107,162%[?12l[?25h[?25l  move(y, x);108,163%[?12l[?25h[?25l  printw("PHY test: %s", good ? "pass" : "fail");109,164%[?12l[?25h[?25l  move(y + 1 + NUM_PORTS, x);110,165%[?12l[?25h[?25l 111,0-165%[?12l[?25h[?25l  return good;112,166%[?12l[?25h[?25l } // phyShowStatusContinuous113,167%[?12l[?25h[?25l 114,0-168%[?12l[?25h[?25l /*115,168%[?12l[?25h[?25l4,0-1[?12l[?25h[?25l3,1 [?12l[?25h[?25l4,0-1[?12l[?25h[?25l5,1 [?12l[?25h[?25l * Stop the interface */116,170%[?12l[?25h[?25l7[?12l[?25h[?25l void phyStopContinuous(void) {118,170%[?12l[?25h[?25l  // Stop the test (and wait for the test to stop)119,171%[?12l[?25h[?25l  writeReg(&nf2, PHY_TEST_CTRL_REG, 0x00000000);120,172%[?12l[?25h[?25l { } // phyStopContinuous121,173%[?12l[?25h[?25l { }122,0-173%[?12l[?25h[?25l /*123,174%[?12l[?25h[?25l  * Get the result of the test124,175%[?12l[?25h[?25l  *125,176%[?12l[?25h[?25l  * Return -- boolean indicating success126,176%[?12l[?25h[?25l  */127,177%[?12l[?25h[?25l int phyGetResult(void) {128,178%[?12l[?25h[?25l  unsigned int val;129,179%[?12l[?25h[?25l  unsigned int port_status;130,179%[?12l[?25h[?25l  unsigned int good_pkts;131,180%[?12l[?25h[?25l  unsigned int bad_pkts;132,181%[?12l[?25h[?25l 133,0-182%[?12l[?25h[?25l  int i;134,182%[?12l[?25h[?25l 135,0-183%[?12l[?25h[?25l  int good = 1;136,184%[?12l[?25h[?25l 137,0-185%[?12l[?25h[?25l  // Read the individual port registers138,185%[?12l[?25h[?25l  for (i = 0; i < NUM_PORTS; i++) {139,186%[?12l[?25h[?25l  // Start with the status register140,187%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_STATUS_REG + i * PHY_TEST_PHY_GROUP_INST_OFFFSET, &port_status);141,188%[?12l[?25h[?25l  if ((port_status & 0x100) == 0) {142,188%[?12l[?25h[?25l  good = 0;143,189%[?12l[?25h[?25l  }144,190%[?12l[?25h[?25l 145,0-191%[?12l[?25h[?25l  // Read the number of good/bad packets146,191%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_GOOD_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INNST_OFFSET, &good_pkts);147,192%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_ERR_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INSST_OFFSET, &bad_pkts);148,193%[?12l[?25h[?25l 149,0-194%[?12l[?25h[?25l  // Update the good flag150,194%[?12l[?25h[?25l49,0-1[?12l[?25h[?25l8,1 [?12l[?25h[?25l7[?12l[?25h[?25l6[?12l[?25h[?25l5,0-1[?12l[?25h[?25l4,1 [?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l1[?12l[?25h[?25l0[?12l[?25h[?25l39[?12l[?25h[?25l8[?12l[?25h[?25l7,0-1[?12l[?25h[?25l6,1 [?12l[?25h[?25l5,0-1[?12l[?25h[?25l4,1 [?12l[?25h[?25l3,0-1[?12l[?25h[?25l2,1 [?12l[?25h[?25l1[?12l[?25h[?25l unsigned int port_status;130,194%[?12l[?25h[?25l unsigned int val;129,193%[?12l[?25h[?25lint phyGetResult(void) {@ 128,192%[?12l[?25h[?25l */127,192%[?12l[?25h[?25l * Return -- boolean indicating success@ 126,191%[?12l[?25h[?25l *125,191%[?12l[?25h[?25l * Get the result of the test124,191%[?12l[?25h[?25l/*123,190%[?12l[?25h[?25l122,0-189%[?12l[?25h[?25l} // phyStopContinuous121,188%[?12l[?25h[?25l2,0-1[?12l[?25h[?25l3,1 [?12l[?25h[?25l4[?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l9[?12l[?25h[?25l30[?12l[?25h[?25l1[?12l[?25h[?25l2[?12l[?25h[?25l3,0-1[?12l[?25h[?25l4,1 [?12l[?25h[?25l5,0-1[?12l[?25h[?25l6,1 [?12l[?25h[?25l7,0-1[?12l[?25h[?25l8,1 [?12l[?25h[?25l9[?12l[?25h[?25l40[?12l[?25h[?25l1[?12l[?25h[?25l2[?12l[?25h[?25l  good = 0;143,189%[?12l[?25h[?25l  }144,190%[?12l[?25h[?25l 145,0-191%[?12l[?25h[?25l  // Read the number of good/bad packets146,191%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_GOOD_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INNST_OFFSET, &good_pkts);147,192%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_ERR_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INSST_OFFSET, &bad_pkts);148,193%[?12l[?25h[?25l 149,0-194%[?12l[?25h[?25l  // Update the good flag150,194%[?12l[?25h[?25l  if (bad_pkts != 0) {151,195%[?12l[?25h[?25l  good = 0;152,196%[?12l[?25h[?25l  }153,197%[?12l[?25h[?25l  }154,197%[?12l[?25h[?25l 155,0-198%[?12l[?25h[?25l  return good;156,199%[?12l[?25h[?25l } // phyGetResult157,1Bot[?12l[?25h[?25l6[?12l[?25h[?25l5,0-1[?12l[?25h[?25l4,1 [?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l1[?12l[?25h[?25l0[?12l[?25h[?25l49,0-1[?12l[?25h[?25l8,1 [?12l[?25h[?25l7[?12l[?25h[?25l6[?12l[?25h[?25l5,0-1[?12l[?25h[?25l4,1 [?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l1[?12l[?25h[?25l0[?12l[?25h[?25l39[?12l[?25h[?25l8[?12l[?25h[?25l137,0-199%[?12l[?25h[?25l int good = 1;136,198%[?12l[?25h[?25l135,0-197%[?12l[?25h[?25l int i;134,197%[?12l[?25h[?25l133,0-196%[?12l[?25h[?25l unsigned int bad_pkts;132,195%[?12l[?25h[?25l unsigned int good_pkts;131,194%[?12l[?25h[?25l2[?12l[?25h[?25l3,0-1[?12l[?25h[?25l4,1 [?12l[?25h[?25l5,0-1[?12l[?25h[?25l6,1 [?12l[?25h[?25l7,0-1[?12l[?25h[?25l8,1 [?12l[?25h[?25l9[?12l[?25h[?25l40[?12l[?25h[?25l1[?12l[?25h[?25l2[?12l[?25h[?25l3[?12l[?25h[?25l4[?12l[?25h[?25l5,0-1[?12l[?25h[?25l6,1 [?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l9,0-1[?12l[?25h[?25l50,1 [?12l[?25h[?25l  if (bad_pkts != 0) {151,195%[?12l[?25h[?25l  good = 0;152,196%[?12l[?25h[?25l  }153,197%[?12l[?25h[?25l  }154,197%[?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l1[?12l[?25h[?25l0[?12l[?25h[?25l49,0-1[?12l[?25h[?25l8,1 [?12l[?25h[?25l7[?12l[?25h[?25l6[?12l[?25h[?25l5,0-1[?12l[?25h[?25l4,1 [?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l1[?12l[?25h[?25l0[?12l[?25h[?25l39[?12l[?25h[?25l8[?12l[?25h[?25l7,0-1[?12l[?25h[?25l6,1 [?12l[?25h[?25l5,0-1[?12l[?25h[?25l int i;134,197%[?12l[?25h[?25l133,0-196%[?12l[?25h[?25l unsigned int bad_pkts;132,195%[?12l[?25h[?25l unsigned int good_pkts;131,194%[?12l[?25h[?25l2[?12l[?25h[?25l3,0-1[?12l[?25h[?25l4,1 [?12l[?25h[?25l5,0-1[?12l[?25h[?25l6,1 [?12l[?25h[?25l7,0-1[?12l[?25h[?25l8,1 [?12l[?25h[?25l9[?12l[?25h[?25l40[?12l[?25h[?25l1[?12l[?25h[?25l2[?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l{}37[?12l[?25h[?25l-- INSERT --143,194% 143,194%{ }[?12l[?25h[?25l2-9[?12l[?25h[?25l1 [?12l[?25h[?25l2-9[?12l[?25h[?25l /3-10[?12l[?25h[?25l//4-11[?12l[?25h[?25l/K5-12[?12l[?25h[?25lKi6-13[?12l[?25h[?25lir7-14[?12l[?25h[?25lra8-15[?12l[?25h[?25lan9-16[?12l[?25h[?25l144,193%[?12l[?25h[?25l2-9[?12l[?25h[?25l p3-10[?12l[?25h[?25lpr4-11[?12l[?25h[?25lri5-12[?12l[?25h[?25lin6-13[?12l[?25h[?25lnt7-14[?12l[?25h[?25ltw8-15[?12l[?25h[?25lw(}9-16[?12l[?25h[?25l(" good = 0; } // Read the number of good/bad packets readReg(&nf2, PHY_TEST_PHY_0_RX_GOOD_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INNST_OFFSET, &good_pkts); readReg(&nf2, PHY_TEST_PHY_0_RX_ERR_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INSST_OFFSET, &bad_pkts);10-17[?12l[?25h[?25l"P1-18[?12l[?25h[?25lPh2-19[?12l[?25h[?25lhy3-20[?12l[?25h[?25lyG4-21[?12l[?25h[?25lGe5-22[?12l[?25h[?25let6-23[?12l[?25h[?25ltR7-24[?12l[?25h[?25lRe8-25[?12l[?25h[?25les9-26[?12l[?25h[?25lsu20-27[?12l[?25h[?25lul1-28[?12l[?25h[?25llt2-29[?12l[?25h[?25l144,21-28 93%[?12l[?25h[?25l3,8-15 [?12l[?25h[?25l2,28 [?12l[?25h[?25l1[?12l[?25h[?25l0[?12l[?25h[?25l39[?12l[?25h[?25l8[?12l[?25h[?25l7,0-1[?12l[?25h[?25l6,15 [?12l[?25h[?25l5,0-1[?12l[?25h[?25l4,8 [?12l[?25h[?25l3,0-1[?12l[?25h[?25l2,24 [?12l[?25h[?25l1,25[?12l[?25h[?25l unsigned int port_status;@ 130,2792%[?12l[?25h[?25l unsigned int val;129,1992%[?12l[?25h[?25lint phyGetResult(void) {@ 128,2492%[?12l[?25h[?25l */127,391%[?12l[?25h[?25l * Return -- boolean indicating success126,2891%[?12l[?25h[?25l *125,290%[?12l[?25h[?25l6,28[?12l[?25h[?25l7,3 [?12l[?25h[?25l8,24[?12l[?25h[?25l9,19[?12l[?25h[?25l30,27[?12l[?25h[?25l1,25[?12l[?25h[?25l2,24[?12l[?25h[?25l3,0-1[?12l[?25h[?25l4,8 [?12l[?25h[?25l5,0-1[?12l[?25h[?25l6,15 [?12l[?25h[?25l7,0-1[?12l[?25h[?25l8,28 [?12l[?25h[?25l9[?12l[?25h[?25l40[?12l[?25h[?25l1[?12l[?25h[?25l2[?12l[?25h[?25l3,8-15[?12l[?25h[?25l4,21-28[?12l[?25h[?25l10-17[?12l[?25h[?25l"p1-18[?12l[?25h[?25l21-2[?12l[?25h[?25l -- INSERT --144,22-29 90%[?12l[?25h[?25lt:3-30[?12l[?25h[?25l 4-31[?12l[?25h[?25l p5-32[?12l[?25h[?25lpo6-33[?12l[?25h[?25lor7-34[?12l[?25h[?25lrt8-35[?12l[?25h[?25l 9-36[?12l[?25h[?25l s30-37[?12l[?25h[?25lst1-38[?12l[?25h[?25lta2-39[?12l[?25h[?25lat3-40[?12l[?25h[?25ltu4-41[?12l[?25h[?25lus5-42[?12l[?25h[?25l 6-43[?12l[?25h[?25l b7-44[?12l[?25h[?25lba8-45[?12l[?25h[?25lad9-46[?12l[?25h[?25ld" good = ; }40-47[?12l[?25h[?25l")}()1-48[?12l[?25h[?25l);()2-49[?12l[?25h[?25l144,41-48 90%[?12l[?25h[?25l5,15 [?12l[?25h[?25l{}6,5 [?12l[?25h[?25l {}147,0-191%[?12l[?25h[?25l  // Read the number of good/bad packets148,4291%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_GOOD_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INNST_OFFSET, &good_pkts);149,4892%[?12l[?25h[?25l readReg(&nf2, PHY_TEST_PHY_0_RX_ERR_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INSST_OFFSET, &bad_pkts);150,4893%[?12l[?25h[?25l 151,0-194%[?12l[?25h[?25l  // Update the good flag152,2794%[?12l[?25h[?25l  if (bad_pkts != 0) {153,2495%[?12l[?25h[?25l2,27[?12l[?25h[?25l3,24[?12l[?25h[?25l  good = 0;154,1596%[?12l[?25h[?25l3,24[?12l[?25h[?25l printw("phyGetResult: port status bad");4,2-95[?12l[?25h[?25lprintw()8-15[?12l[?25h[?25l()10-17[?12l[?25h[?25l22-29[?12l[?25h[?25l4-31[?12l[?25h[?25l ort status bad");[?12l[?25h[?25l rt status bad");[?12l[?25h[?25l t status bad");[?12l[?25h[?25l status bad");[?12l[?25h[?25l status bad");[?12l[?25h[?25l tatus bad");[?12l[?25h[?25l atus bad");[?12l[?25h[?25l tus bad");[?12l[?25h[?25l us bad");[?12l[?25h[?25l s bad");[?12l[?25h[?25l bad");[?12l[?25h[?25l bad");[?12l[?25h[?25l -- INSERT --154,24-31 95%[?12l[?25h[?25l fbad");5-32[?12l[?25h[?25lfobad");6-33[?12l[?25h[?25loubad");7-34[?12l[?25h[?25lunbad");8-35[?12l[?25h[?25lndbad");9-36[?12l[?25h[?25ld bad");30-37[?12l[?25h[?25l154,29-36 95%[?12l[?25h[?25l30-37[?12l[?25h[?25l1-38[?12l[?25h[?25l2-39[?12l[?25h[?25l3-40[?12l[?25h[?25l -- INSERT --154,33-40 95%[?12l[?25h[?25ld ");4-41[?12l[?25h[?25l p");5-42[?12l[?25h[?25lpa");6-43[?12l[?25h[?25lac");7-44[?12l[?25h[?25lck");8-45[?12l[?25h[?25lke");9-46[?12l[?25h[?25let");40-47[?12l[?25h[?25lts");1-48[?12l[?25h[?25l154,40-47 95%[?12l[?25h[?25l:[?12l[?25hw[?25l[?12l[?25h [?25l"selftest_phy.c" 160L, 4050C written154,40-47 95%154,40-47 95%[?12l[?25h[?25l  good = 0;155,1596%[?12l[?25h[?25l { }156,597%[?12l[?25h[?25l {{} }157,397%[?12l[?25h[?25l {}158,0-198%[?12l[?25h[?25l  return good;159,1499%[?12l[?25h[?25l } // phyGetResult160,17Bot[?12l[?25h[?25l59,14[?12l[?25h[?25l8,0-1[?12l[?25h[?25l7,3 [?12l[?25h[?25l{}6,5[?12l[?25h[?25l{}5,15[?12l[?25h[?25l4,40-47[?12l[?25h[?25l{}3,24 [?12l[?25h[?25l{}2,27[?12l[?25h[?25l{}3,24[?12l[?25h[?25l{}4,40-47[?12l[?25h[?25l5,15 [?12l[?25h[?25l{}6,5 [?12l[?25h[?25l{}7,3[?12l[?25h[?25l:[?12l[?25hw[?25l[?12l[?25hq[?25l[?12l[?25h [?25l"selftest_phy.c" 160L, 4050C written [?1l>[?12l[?25h[?1049l ]0;root@node1-1: ~/netfpga/projects/selftest/swroot@node1-1:~/netfpga/projects/selftest/sw# make /bin/nf_register_gen.pl --project selftest make: /bin/nf_register_gen.pl: Command not found make: *** [registers] Error 127 ]0;root@node1-1: ~/netfpga/projects/selftest/swroot@node1-1:~/netfpga/projects/selftest/sw# ls -l total 328 -rwxr-xr-x 1 netfpga netfpga 26966 2011-03-09 19:22 bad_pkt_dump -rw-r--r-- 1 netfpga netfpga 2386 2011-03-09 18:24 bad_pkt_dump.c -rw-r--r-- 1 netfpga netfpga 4296 2011-03-09 19:22 bad_pkt_dump.o -rw-r--r-- 1 netfpga netfpga 903 2011-03-09 18:24 Makefile -rw-r--r-- 1 netfpga netfpga 3212 2011-03-09 18:24 or_data_types.h -rw-r--r-- 1 netfpga netfpga 731 2011-03-09 18:24 or_ip.c -rw-r--r-- 1 netfpga netfpga 129 2011-03-09 18:24 or_ip.h -rw-r--r-- 1 netfpga netfpga 3464 2011-03-09 19:22 or_ip.o -rw-r--r-- 1 netfpga netfpga 872 2011-03-09 18:24 or_utils.c -rw-r--r-- 1 netfpga netfpga 292 2011-03-09 18:24 or_utils.h -rw-r--r-- 1 netfpga netfpga 4108 2011-03-09 19:22 or_utils.o -rwxr-xr-x 1 netfpga netfpga 67122 2011-03-09 19:22 selftest -rw-r--r-- 1 netfpga netfpga 10370 2011-03-09 18:24 selftest.c -rw-r--r-- 1 netfpga netfpga 3581 2011-03-09 18:24 selftest_clk.c -rw-r--r-- 1 netfpga netfpga 516 2011-03-09 18:24 selftest_clk.h -rw-r--r-- 1 netfpga netfpga 5740 2011-03-09 19:22 selftest_clk.o -rw-r--r-- 1 netfpga netfpga 6094 2011-03-09 18:24 selftest_dma.c -rw-r--r-- 1 netfpga netfpga 644 2011-03-09 18:24 selftest_dma.h -rw-r--r-- 1 netfpga netfpga 11516 2011-03-09 19:22 selftest_dma.o -rw-r--r-- 1 netfpga netfpga 2660 2011-03-09 18:24 selftest_dram.c -rw-r--r-- 1 netfpga netfpga 554 2011-03-09 18:24 selftest_dram.h -rw-r--r-- 1 netfpga netfpga 4844 2011-03-09 19:22 selftest_dram.o -rw-r--r-- 1 netfpga netfpga 859 2011-03-09 18:24 selftest.h -rw-r--r-- 1 netfpga netfpga 4628 2011-03-09 18:24 selftest_mdio.c -rw-r--r-- 1 netfpga netfpga 526 2011-03-09 18:24 selftest_mdio.h -rw-r--r-- 1 netfpga netfpga 7932 2011-03-09 19:22 selftest_mdio.o -rw-r--r-- 1 netfpga netfpga 17076 2011-03-09 19:22 selftest.o -rw-r--r-- 1 netfpga netfpga 4050 2011-03-10 15:13 selftest_phy.c -rw-r--r-- 1 netfpga netfpga 487 2011-03-09 18:24 selftest_phy.h -rw-r--r-- 1 netfpga netfpga 6612 2011-03-09 19:22 selftest_phy.o -rw-r--r-- 1 netfpga netfpga 1933 2011-03-09 18:24 selftest_reg.c -rw-r--r-- 1 netfpga netfpga 520 2011-03-09 18:24 selftest_reg.h -rw-r--r-- 1 netfpga netfpga 4100 2011-03-09 19:22 selftest_reg.o -rw-r--r-- 1 netfpga netfpga 5986 2011-03-09 18:24 selftest_serial.c -rw-r--r-- 1 netfpga netfpga 512 2011-03-09 18:24 selftest_serial.h -rw-r--r-- 1 netfpga netfpga 6608 2011-03-09 19:22 selftest_serial.o -rw-r--r-- 1 netfpga netfpga 3258 2011-03-09 18:24 selftest_sram.c -rw-r--r-- 1 netfpga netfpga 564 2011-03-09 18:24 selftest_sram.h -rw-r--r-- 1 netfpga netfpga 4976 2011-03-09 19:22 selftest_sram.o ]0;root@node1-1: ~/netfpga/projects/selftest/swroot@node1-1:~/netfpga/projects/selftest/sw# ]0;root@node1-1: ~/netfpga/projects/selftest/swroot@node1-1:~/netfpga/projects/selftest/sw# ./bad_pkt_dump Found net device: nf2c0 Expected data: 00000000: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000010: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000020: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000030: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000040: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000050: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000060: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000070: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000080: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000090: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000000a0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000000b0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000000c0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000000d0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000000e0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000000f0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000100: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000110: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000120: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000130: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000140: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000150: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000160: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000170: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000180: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000190: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000001a0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000001b0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000001c0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000001d0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000001e0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000001f0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000200: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000210: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000220: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000230: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000240: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000250: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000260: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000270: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000280: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000290: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000002a0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000002b0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000002c0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000002d0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000002e0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000002f0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000300: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000310: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000320: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000330: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000340: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000350: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000360: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000370: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000380: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000390: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000003a0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000003b0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000003c0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000003d0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000003e0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000003f0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000400: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000410: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000420: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000430: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000440: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000450: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000460: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000470: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000480: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000490: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000004a0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000004b0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000004c0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000004d0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000004e0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000004f0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000500: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000510: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000520: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000530: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000540: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000550: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000560: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000570: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000580: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000590: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000005a0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000005b0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000005c0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000005d0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000005e0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 Received data: 00000000: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000010: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000020: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000030: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000040: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000050: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000060: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000070: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000080: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000090: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000000a0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000000b0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000000c0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000000d0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000000e0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000000f0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000100: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000110: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000120: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000130: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000140: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000150: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000160: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000170: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000180: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000190: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000001a0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000001b0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000001c0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000001d0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000001e0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000001f0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000200: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000210: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000220: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000230: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000240: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000250: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000260: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000270: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000280: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000290: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000002a0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000002b0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000002c0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000002d0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000002e0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000002f0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000300: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000310: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000320: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000330: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000340: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000350: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000360: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000370: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000380: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000390: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000003a0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000003b0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000003c0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000003d0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000003e0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000003f0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000400: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000410: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000420: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000430: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000440: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000450: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000460: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000470: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000480: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000490: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000004a0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000004b0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000004c0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000004d0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000004e0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000004f0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000500: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000510: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000520: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000530: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000540: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000550: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000560: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000570: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000580: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 00000590: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000005a0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000005b0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000005c0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000005d0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 00 ca fe 00 000005e0: 00 ca fe 00 00 ca fe 00 00 ca fe 00 ]0;root@node1-1: ~/netfpga/projects/selftest/swroot@node1-1:~/netfpga/projects/selftest/sw# ls bad_pkt_dump or_ip.c or_utils.o selftest_clk.o selftest_dram.h selftest_mdio.o selftest_reg.c selftest_serial.o bad_pkt_dump.c or_ip.h selftest selftest_dma.c selftest_dram.o selftest.o selftest_reg.h selftest_sram.c bad_pkt_dump.o or_ip.o selftest.c selftest_dma.h selftest.h selftest_phy.c selftest_reg.o selftest_sram.h Makefile or_utils.c selftest_clk.c selftest_dma.o selftest_mdio.c selftest_phy.h selftest_serial.c selftest_sram.o or_data_types.h or_utils.h selftest_clk.h selftest_dram.c selftest_mdio.h selftest_phy.o selftest_serial.h ]0;root@node1-1: ~/netfpga/projects/selftest/swroot@node1-1:~/netfpga/projects/selftest/sw# cd exit exit ]0;netfpga@node1-1: ~netfpga@node1-1:~$ ls netfpga pkgs ]0;netfpga@node1-1: ~netfpga@node1-1:~$ cd netfpga/ ]0;netfpga@node1-1: ~/netfpganetfpga@node1-1:~/netfpga$ ls bashrc_addon bin bitfiles CHANGES doc lib LICENSE Makefile projects README ]0;netfpga@node1-1: ~/netfpganetfpga@node1-1:~/netfpga$ makecd make echo /home/netfpga/netfpga/lib/Perl5: /home/netfpga/netfpga/lib/Perl5: if [ -f "lib/Makefile" ] ; then \ make -C lib ; \ fi make[1]: Entering directory `/home/netfpga/netfpga/lib' make -C C make[2]: Entering directory `/home/netfpga/netfpga/lib/C' make -C kernel make[3]: Entering directory `/home/netfpga/netfpga/lib/C/kernel' make -C /lib/modules/2.6.31-19-generic/build M=/home/netfpga/netfpga/lib/C/kernel LDDINC=/home/netfpga/netfpga/lib/C/kernel/../include modules make[4]: Entering directory `/usr/src/linux-headers-2.6.31-19-generic' Building modules, stage 2. MODPOST 1 modules make[4]: Leaving directory `/usr/src/linux-headers-2.6.31-19-generic' make[3]: Leaving directory `/home/netfpga/netfpga/lib/C/kernel' make -C download make[3]: Entering directory `/home/netfpga/netfpga/lib/C/download' make -C ../common make[4]: Entering directory `/home/netfpga/netfpga/lib/C/common' make[4]: Nothing to be done for `all'. make[4]: Leaving directory `/home/netfpga/netfpga/lib/C/common' make[3]: Leaving directory `/home/netfpga/netfpga/lib/C/download' make -C reg_access make[3]: Entering directory `/home/netfpga/netfpga/lib/C/reg_access' make -C ../common make[4]: Entering directory `/home/netfpga/netfpga/lib/C/common' make[4]: Nothing to be done for `all'. make[4]: Leaving directory `/home/netfpga/netfpga/lib/C/common' make[3]: Leaving directory `/home/netfpga/netfpga/lib/C/reg_access' make -C tools make[3]: Entering directory `/home/netfpga/netfpga/lib/C/tools' make -C nf_info make[4]: Entering directory `/home/netfpga/netfpga/lib/C/tools/nf_info' make -C ../../common make[5]: Entering directory `/home/netfpga/netfpga/lib/C/common' make[5]: Nothing to be done for `all'. make[5]: Leaving directory `/home/netfpga/netfpga/lib/C/common' make[4]: Leaving directory `/home/netfpga/netfpga/lib/C/tools/nf_info' make[3]: Leaving directory `/home/netfpga/netfpga/lib/C/tools' make[2]: Leaving directory `/home/netfpga/netfpga/lib/C' make -C scripts make[2]: Entering directory `/home/netfpga/netfpga/lib/scripts' make -C cpci_reprogram make[3]: Entering directory `/home/netfpga/netfpga/lib/scripts/cpci_reprogram' make[3]: Nothing to be done for `all'. make[3]: Leaving directory `/home/netfpga/netfpga/lib/scripts/cpci_reprogram' make -C cpci_config_reg_access make[3]: Entering directory `/home/netfpga/netfpga/lib/scripts/cpci_config_reg_access' make[3]: Nothing to be done for `all'. make[3]: Leaving directory `/home/netfpga/netfpga/lib/scripts/cpci_config_reg_access' make[2]: Leaving directory `/home/netfpga/netfpga/lib/scripts' make[1]: Leaving directory `/home/netfpga/netfpga/lib' echo /home/netfpga/netfpga/lib/Perl5: /home/netfpga/netfpga/lib/Perl5: if [ -f "bitfiles/Makefile" ] ; then \ make -C bitfiles ; \ fi make[1]: Entering directory `/home/netfpga/netfpga/bitfiles' make[1]: Nothing to be done for `all'. make[1]: Leaving directory `/home/netfpga/netfpga/bitfiles' echo /home/netfpga/netfpga/lib/Perl5: /home/netfpga/netfpga/lib/Perl5: if [ -f "projects/Makefile" ] ; then \ make -C projects ; \ fi make[1]: Entering directory `/home/netfpga/netfpga/projects' make -C reference_nic make[2]: Entering directory `/home/netfpga/netfpga/projects/reference_nic' make -C sw make[3]: Entering directory `/home/netfpga/netfpga/projects/reference_nic/sw' /home/netfpga/netfpga/bin/nf_register_gen.pl --project reference_nic NetFPGA environment: Root dir: /home/netfpga/netfpga Project name: reference_nic Project dir: /home/netfpga/netfpga/projects/reference_nic Work dir: /tmp/netfpga Processing /home/netfpga/netfpga/lib/verilog/core/common/xml/global.xml... Processing /home/netfpga/netfpga/lib/verilog/core/common/xml/nf_defines.xml... Processing /home/netfpga/netfpga/projects/reference_nic/include/project.xml... Project: 'Reference NIC' (reference_nic) Description: Reference NIC Version: 1.1.0 Device ID: 1 Processing /home/netfpga/netfpga/lib/verilog/core/io_queues/cpu_dma_queue/xml/cpu_dma_queue.xml... Processing /home/netfpga/netfpga/lib/verilog/core/io_queues/ethernet_queue/xml/ethernet_mac.xml... WARNING: No module specific XML found for module 'contrib/ucsd/gig_eth_mac' Processing /home/netfpga/netfpga/lib/verilog/core/input_arbiter/rr_input_arbiter/xml/rr_input_arbiter.xml... WARNING: No module specific XML found for module 'core/nf2/generic_top' WARNING: No module specific XML found for module 'core/nf2/reference_core' WARNING: No module specific XML found for module 'core/output_port_lookup/nic' Processing /home/netfpga/netfpga/lib/verilog/core/output_queues/sram_rr_output_queues/xml/sram_rr_output_queues.xml... WARNING: No module specific XML found for module 'core/sram_arbiter/sram_weighted_rr' WARNING: No module specific XML found for module 'core/user_data_path/reference_user_data_path' Processing /home/netfpga/netfpga/lib/verilog/core/io/mdio/xml/mdio.xml... WARNING: No module specific XML found for module 'core/cpci_bus' Processing /home/netfpga/netfpga/lib/verilog/core/dma/xml/dma.xml... WARNING: No module specific XML found for module 'core/user_data_path/udp_reg_master' WARNING: No module specific XML found for module 'core/io_queues/add_rm_hdr' Processing /home/netfpga/netfpga/lib/verilog/core/strip_headers/keep_length/xml/strip_headers.xml... Processing /home/netfpga/netfpga/lib/verilog/core/utils/xml/device_id_reg.xml... WARNING: No module specific XML found for module 'core/utils/generic_regs' make[3]: Leaving directory `/home/netfpga/netfpga/projects/reference_nic/sw' make[2]: Leaving directory `/home/netfpga/netfpga/projects/reference_nic' make -C reference_router make[2]: Entering directory `/home/netfpga/netfpga/projects/reference_router' make -C sw make[3]: Entering directory `/home/netfpga/netfpga/projects/reference_router/sw' /home/netfpga/netfpga/bin/nf_register_gen.pl --project reference_router NetFPGA environment: Root dir: /home/netfpga/netfpga Project name: reference_router Project dir: /home/netfpga/netfpga/projects/reference_router Work dir: /tmp/netfpga Processing /home/netfpga/netfpga/lib/verilog/core/common/xml/global.xml... Processing /home/netfpga/netfpga/lib/verilog/core/common/xml/nf_defines.xml... Processing /home/netfpga/netfpga/projects/reference_router/include/project.xml... Project: 'Reference router' (reference_router) Description: Reference IPv4 router Version: 1.0.0 Device ID: 2 Processing /home/netfpga/netfpga/lib/verilog/core/io_queues/cpu_dma_queue/xml/cpu_dma_queue.xml... Processing /home/netfpga/netfpga/lib/verilog/core/io_queues/ethernet_queue/xml/ethernet_mac.xml... WARNING: No module specific XML found for module 'contrib/ucsd/gig_eth_mac' Processing /home/netfpga/netfpga/lib/verilog/core/input_arbiter/rr_input_arbiter/xml/rr_input_arbiter.xml... WARNING: No module specific XML found for module 'core/nf2/generic_top' WARNING: No module specific XML found for module 'core/nf2/reference_core' Processing /home/netfpga/netfpga/lib/verilog/core/output_port_lookup/cam_router/xml/cam_router.xml... Processing /home/netfpga/netfpga/lib/verilog/core/output_queues/sram_rr_output_queues/xml/sram_rr_output_queues.xml... WARNING: No module specific XML found for module 'core/sram_arbiter/sram_weighted_rr' WARNING: No module specific XML found for module 'core/user_data_path/reference_user_data_path' Processing /home/netfpga/netfpga/lib/verilog/core/io/mdio/xml/mdio.xml... WARNING: No module specific XML found for module 'core/cpci_bus' Processing /home/netfpga/netfpga/lib/verilog/core/dma/xml/dma.xml... WARNING: No module specific XML found for module 'core/user_data_path/udp_reg_master' WARNING: No module specific XML found for module 'core/io_queues/add_rm_hdr' Processing /home/netfpga/netfpga/lib/verilog/core/strip_headers/keep_length/xml/strip_headers.xml... Processing /home/netfpga/netfpga/lib/verilog/core/utils/xml/device_id_reg.xml... WARNING: No module specific XML found for module 'core/utils/generic_regs' make[3]: Leaving directory `/home/netfpga/netfpga/projects/reference_router/sw' make[2]: Leaving directory `/home/netfpga/netfpga/projects/reference_router' make -C reference_switch make[2]: Entering directory `/home/netfpga/netfpga/projects/reference_switch' make -C sw make[3]: Entering directory `/home/netfpga/netfpga/projects/reference_switch/sw' /home/netfpga/netfpga/bin/nf_register_gen.pl --project reference_switch NetFPGA environment: Root dir: /home/netfpga/netfpga Project name: reference_switch Project dir: /home/netfpga/netfpga/projects/reference_switch Work dir: /tmp/netfpga Processing /home/netfpga/netfpga/lib/verilog/core/common/xml/global.xml... Processing /home/netfpga/netfpga/lib/verilog/core/common/xml/nf_defines.xml... Processing /home/netfpga/netfpga/projects/reference_switch/include/project.xml... Project: 'Reference Switch' (reference_switch) Description: Reference Switch Version: 1.0.0 Device ID: 3 Processing /home/netfpga/netfpga/lib/verilog/core/io_queues/cpu_dma_queue/xml/cpu_dma_queue.xml... Processing /home/netfpga/netfpga/lib/verilog/core/io_queues/ethernet_queue/xml/ethernet_mac.xml... WARNING: No module specific XML found for module 'contrib/ucsd/gig_eth_mac' Processing /home/netfpga/netfpga/lib/verilog/core/input_arbiter/rr_input_arbiter/xml/rr_input_arbiter.xml... WARNING: No module specific XML found for module 'core/nf2/generic_top' WARNING: No module specific XML found for module 'core/nf2/reference_core' Processing /home/netfpga/netfpga/lib/verilog/core/output_port_lookup/learning_cam_switch/xml/learning_cam_switch.xml... Processing /home/netfpga/netfpga/lib/verilog/core/output_queues/sram_rr_output_queues/xml/sram_rr_output_queues.xml... WARNING: No module specific XML found for module 'core/sram_arbiter/sram_weighted_rr' WARNING: No module specific XML found for module 'core/user_data_path/reference_user_data_path' WARNING: No module specific XML found for module 'core/user_data_path/udp_reg_master' Processing /home/netfpga/netfpga/lib/verilog/core/io/mdio/xml/mdio.xml... WARNING: No module specific XML found for module 'core/cpci_bus' Processing /home/netfpga/netfpga/lib/verilog/core/dma/xml/dma.xml... WARNING: No module specific XML found for module 'core/io_queues/add_rm_hdr' Processing /home/netfpga/netfpga/lib/verilog/core/strip_headers/keep_length/xml/strip_headers.xml... Processing /home/netfpga/netfpga/lib/verilog/core/utils/xml/device_id_reg.xml... make[3]: Leaving directory `/home/netfpga/netfpga/projects/reference_switch/sw' make[2]: Leaving directory `/home/netfpga/netfpga/projects/reference_switch' make -C router_buffer_sizing make[2]: Entering directory `/home/netfpga/netfpga/projects/router_buffer_sizing' make -C sw make[3]: Entering directory `/home/netfpga/netfpga/projects/router_buffer_sizing/sw' make[3]: Nothing to be done for `all'. make[3]: Leaving directory `/home/netfpga/netfpga/projects/router_buffer_sizing/sw' make[2]: Leaving directory `/home/netfpga/netfpga/projects/router_buffer_sizing' make -C router_kit make[2]: Entering directory `/home/netfpga/netfpga/projects/router_kit' make -C sw make[3]: Entering directory `/home/netfpga/netfpga/projects/router_kit/sw' /home/netfpga/netfpga/bin/nf_register_gen.pl --project reference_router NetFPGA environment: Root dir: /home/netfpga/netfpga Project name: reference_router Project dir: /home/netfpga/netfpga/projects/reference_router Work dir: /tmp/netfpga Processing /home/netfpga/netfpga/lib/verilog/core/common/xml/global.xml... Processing /home/netfpga/netfpga/lib/verilog/core/common/xml/nf_defines.xml... Processing /home/netfpga/netfpga/projects/reference_router/include/project.xml... Project: 'Reference router' (reference_router) Description: Reference IPv4 router Version: 1.0.0 Device ID: 2 Processing /home/netfpga/netfpga/lib/verilog/core/io_queues/cpu_dma_queue/xml/cpu_dma_queue.xml... Processing /home/netfpga/netfpga/lib/verilog/core/io_queues/ethernet_queue/xml/ethernet_mac.xml... WARNING: No module specific XML found for module 'contrib/ucsd/gig_eth_mac' Processing /home/netfpga/netfpga/lib/verilog/core/input_arbiter/rr_input_arbiter/xml/rr_input_arbiter.xml... WARNING: No module specific XML found for module 'core/nf2/generic_top' WARNING: No module specific XML found for module 'core/nf2/reference_core' Processing /home/netfpga/netfpga/lib/verilog/core/output_port_lookup/cam_router/xml/cam_router.xml... Processing /home/netfpga/netfpga/lib/verilog/core/output_queues/sram_rr_output_queues/xml/sram_rr_output_queues.xml... WARNING: No module specific XML found for module 'core/sram_arbiter/sram_weighted_rr' WARNING: No module specific XML found for module 'core/user_data_path/reference_user_data_path' Processing /home/netfpga/netfpga/lib/verilog/core/io/mdio/xml/mdio.xml... WARNING: No module specific XML found for module 'core/cpci_bus' Processing /home/netfpga/netfpga/lib/verilog/core/dma/xml/dma.xml... WARNING: No module specific XML found for module 'core/user_data_path/udp_reg_master' WARNING: No module specific XML found for module 'core/io_queues/add_rm_hdr' Processing /home/netfpga/netfpga/lib/verilog/core/strip_headers/keep_length/xml/strip_headers.xml... Processing /home/netfpga/netfpga/lib/verilog/core/utils/xml/device_id_reg.xml... WARNING: No module specific XML found for module 'core/utils/generic_regs' ln -f -s ../../reference_router/lib/C/reg_defines_reference_router.h reg_defines.h make[3]: Leaving directory `/home/netfpga/netfpga/projects/router_kit/sw' make[2]: Leaving directory `/home/netfpga/netfpga/projects/router_kit' make -C scone make[2]: Entering directory `/home/netfpga/netfpga/projects/scone' make -C sw make[3]: Entering directory `/home/netfpga/netfpga/projects/scone/sw' /home/netfpga/netfpga/bin/nf_register_gen.pl --project reference_router NetFPGA environment: Root dir: /home/netfpga/netfpga Project name: reference_router Project dir: /home/netfpga/netfpga/projects/reference_router Work dir: /tmp/netfpga Processing /home/netfpga/netfpga/lib/verilog/core/common/xml/global.xml... Processing /home/netfpga/netfpga/lib/verilog/core/common/xml/nf_defines.xml... Processing /home/netfpga/netfpga/projects/reference_router/include/project.xml... Project: 'Reference router' (reference_router) Description: Reference IPv4 router Version: 1.0.0 Device ID: 2 Processing /home/netfpga/netfpga/lib/verilog/core/io_queues/cpu_dma_queue/xml/cpu_dma_queue.xml... Processing /home/netfpga/netfpga/lib/verilog/core/io_queues/ethernet_queue/xml/ethernet_mac.xml... WARNING: No module specific XML found for module 'contrib/ucsd/gig_eth_mac' Processing /home/netfpga/netfpga/lib/verilog/core/input_arbiter/rr_input_arbiter/xml/rr_input_arbiter.xml... WARNING: No module specific XML found for module 'core/nf2/generic_top' WARNING: No module specific XML found for module 'core/nf2/reference_core' Processing /home/netfpga/netfpga/lib/verilog/core/output_port_lookup/cam_router/xml/cam_router.xml... Processing /home/netfpga/netfpga/lib/verilog/core/output_queues/sram_rr_output_queues/xml/sram_rr_output_queues.xml... WARNING: No module specific XML found for module 'core/sram_arbiter/sram_weighted_rr' WARNING: No module specific XML found for module 'core/user_data_path/reference_user_data_path' Processing /home/netfpga/netfpga/lib/verilog/core/io/mdio/xml/mdio.xml... WARNING: No module specific XML found for module 'core/cpci_bus' Processing /home/netfpga/netfpga/lib/verilog/core/dma/xml/dma.xml... WARNING: No module specific XML found for module 'core/user_data_path/udp_reg_master' WARNING: No module specific XML found for module 'core/io_queues/add_rm_hdr' Processing /home/netfpga/netfpga/lib/verilog/core/strip_headers/keep_length/xml/strip_headers.xml... Processing /home/netfpga/netfpga/lib/verilog/core/utils/xml/device_id_reg.xml... WARNING: No module specific XML found for module 'core/utils/generic_regs' ln -f -s /home/netfpga/netfpga/projects/reference_router/lib/C/reg_defines_reference_router.h reg_defines.h make[3]: Leaving directory `/home/netfpga/netfpga/projects/scone/sw' make[2]: Leaving directory `/home/netfpga/netfpga/projects/scone' make -C selftest make[2]: Entering directory `/home/netfpga/netfpga/projects/selftest' make -C sw make[3]: Entering directory `/home/netfpga/netfpga/projects/selftest/sw' /home/netfpga/netfpga/bin/nf_register_gen.pl --project selftest NetFPGA environment: Root dir: /home/netfpga/netfpga Project name: selftest Project dir: /home/netfpga/netfpga/projects/selftest Work dir: /tmp/netfpga Processing /home/netfpga/netfpga/lib/verilog/core/common/xml/global.xml... Processing /home/netfpga/netfpga/lib/verilog/core/common/xml/nf_defines.xml... Processing /home/netfpga/netfpga/projects/selftest/include/project.xml... Project: 'Selftest' (selftest) Description: NetFPGA selftest -- exercises all major subsystems of the board Version: 1.1.0 Device ID: 5 WARNING: No module specific XML found for module 'core/nf2/reference_core' Processing /home/netfpga/netfpga/lib/verilog/core/io/mdio/xml/mdio.xml... WARNING: No module specific XML found for module 'core/cpci_bus' Processing /home/netfpga/netfpga/lib/verilog/core/dma/xml/dma.xml... WARNING: No module specific XML found for module 'core/ddr2_controller' Processing /home/netfpga/netfpga/lib/verilog/core/utils/xml/device_id_reg.xml... Processing /home/netfpga/netfpga/projects/selftest/include/clock_test.xml... Processing /home/netfpga/netfpga/projects/selftest/include/dram_test.xml... Processing /home/netfpga/netfpga/projects/selftest/include/phy_test.xml... Processing /home/netfpga/netfpga/projects/selftest/include/reg_file.xml... Processing /home/netfpga/netfpga/projects/selftest/include/reg_reflect.xml... Processing /home/netfpga/netfpga/projects/selftest/include/serial_test.xml... Processing /home/netfpga/netfpga/projects/selftest/include/sram_msb.xml... Processing /home/netfpga/netfpga/projects/selftest/include/sram_test.xml... /home/netfpga/netfpga/bin/nf_register_gen.pl --project cpci NetFPGA environment: Root dir: /home/netfpga/netfpga Project name: cpci Project dir: /home/netfpga/netfpga/projects/cpci Work dir: /tmp/netfpga Processing /home/netfpga/netfpga/lib/verilog/core/common/xml/global.xml... Processing /home/netfpga/netfpga/lib/verilog/core/common/xml/nf_defines.xml... Processing /home/netfpga/netfpga/projects/cpci/include/project.xml... Project: 'CPCI' (cpci) Description: NetFPGA PCI interface Version: 4.1.0 Device ID: 0 Processing /home/netfpga/netfpga/projects/cpci/include/cpci_regs.xml... gcc -g -c -o selftest_phy.o selftest_phy.c gcc -lncurses selftest.o selftest_dram.o selftest_sram.o selftest_serial.o selftest_phy.o selftest_mdio.o selftest_reg.o selftest_clk.o selftest_dma.o or_ip.o or_utils.o /home/netfpga/netfpga/lib/C/common/nf2util.o /home/netfpga/netfpga/lib/C/common/nf2util_proxy_common.o -o selftest make[3]: Leaving directory `/home/netfpga/netfpga/projects/selftest/sw' make[2]: Leaving directory `/home/netfpga/netfpga/projects/selftest' make[1]: Leaving directory `/home/netfpga/netfpga/projects' ]0;netfpga@node1-1: ~/netfpganetfpga@node1-1:~/netfpga$ sudo bash ]0;root@node1-1: ~/netfpgaroot@node1-1:~/netfpga# exitls./bad_pkt_dump ls -lmakevi selftest_phy.c ./selftest -nvi selftest_phy.c .cgrep PHY * | morelsvi selftest_phy.c lscd netfpga/projects/selftest/sw/ lsess netfpga/projects/selftest/sw/selftest netfpga/projects/selftest/sw/selftest -n less netfpga/projects/selftest/sw/selftest netfpga/projects/selftest/sw/selftest -n projects/selftest/sw/projects/selftest/sw/projects/selftest/sw/rojects/selftest/sw/projects/selftest/sw/projects/selftest/sw/projects/selftest/sw/projects/selftest/sw/cprojects/selftest/sw/dprojects/selftest/sw/ projects/selftest/sw/ ]0;root@node1-1: ~/netfpga/projects/selftest/swroot@node1-1:~/netfpga/projects/selftest/sw# ./selftest -n Found net device: nf2c0 CPCI Information ---------------- Version: 4 (rev 1) Device (Virtex) Information --------------------------- Project directory: selftest Project name: Selftest Project description: NetFPGA selftest -- exercises all major subsystems of the board Device ID: 5 Version: 1.1.0 Built against CPCI version: 4 (rev 1) NetFPGA selftest 1.00 alpha Running.....Segmentation fault ]0;root@node1-1: ~/netfpga/projects/selftest/swroot@node1-1:~/netfpga/projects/selftest/sw# exit exit ]0;netfpga@node1-1: ~/netfpganetfpga@node1-1:~/netfpga$ sudo bashcd -prijpojects/selftest/ include/ lib/ src/ sw/ synth/ verif/ ]0;netfpga@node1-1: ~/netfpganetfpga@node1-1:~/netfpga$ cd projects/selftest/src/srsw/ ]0;netfpga@node1-1: ~/netfpga/projects/selftest/swnetfpga@node1-1:~/netfpga/projects/selftest/sw$ ls bad_pkt_dump or_ip.c or_utils.o selftest_clk.o selftest_dram.h selftest_mdio.o selftest_reg.c selftest_serial.o bad_pkt_dump.c or_ip.h selftest selftest_dma.c selftest_dram.o selftest.o selftest_reg.h selftest_sram.c bad_pkt_dump.o or_ip.o selftest.c selftest_dma.h selftest.h selftest_phy.c selftest_reg.o selftest_sram.h Makefile or_utils.c selftest_clk.c selftest_dma.o selftest_mdio.c selftest_phy.h selftest_serial.c selftest_sram.o or_data_types.h or_utils.h selftest_clk.h selftest_dram.c selftest_mdio.h selftest_phy.o selftest_serial.h ]0;netfpga@node1-1: ~/netfpga/projects/selftest/swnetfpga@node1-1:~/netfpga/projects/selftest/sw$ vi selftest.-_phy.c [?1049h[?1h=[?12;25h[?12l[?25h[?25l"selftest_phy.c" 160L, 4050C[>c/* **************************************************************************** * vim:set shiftwidth=2 softtabstop=2 expandtab: * $Id: selftest_phy.c 5971 2010-03-06 06:44:56Z grg $ * * Module: selftest_phy.c * Project: NetFPGA selftest * Description: SATA selftest module * * Change history: * */ #include "../lib/C/reg_defines_selftest.h" #include "selftest.h" #include "selftest_phy.h" #include  #include  #define NUM_PORTS 4 static int prev_good_pkts[NUM_PORTS]; static int prev_bad_pkts[NUM_PORTS]; /* * Reset the interface and configure it for continuous operation */ void phyResetContinuous(void) { int i; for (i = 0; i < NUM_PORTS; i++) { prev_good_pkts[i] = 0; prev_bad_pkts[i] = 0; } // Stop the test (and wait for the test to stop) writeReg(&nf2, PHY_TEST_CTRL_REG, 0x0); sleep(1); writeReg(&nf2, PHY_TEST_PATTERN_REG, PHY_TEST_PATTERN_ENABLE_MASK); // Start the test writeReg(&nf2, PHY_TEST_CTRL_REG, PHY_TEST_CTRL_REPEAT); } // phyResetContinuous1,1Top[?12l[?25hP+q436f\P+q6b75\P+q6b64\P+q6b72\P+q6b6c\P+q2332\P+q2334\P+q2569\P+q2a37\P+q6b31\P+q6b32\[?25l/* **************************************************************************** * vim:set shiftwidth=2 softtabstop=2 expandtab: * $Id: selftest_phy.c 5971 2010-03-06 06:44:56Z grg $ * * Module: selftest_phy.c * Project: NetFPGA selftest * Description: SATA selftest module * * Change history: * */ #include "../lib/C/reg_defines_selftest.h" #include "selftest.h" #include "selftest_phy.h" #include  #include  #define NUM_PORTS 4 static int prev_good_pkts[NUM_PORTS]; static int prev_bad_pkts[NUM_PORTS]; /* * Reset the interface and configure it for continuous operation */ void phyResetContinuous(void) { int i; for (i = 0; i < NUM_PORTS; i++) { prev_good_pkts[i] = 0; prev_bad_pkts[i] = 0; } // Stop the test (and wait for the test to stop) writeReg(&nf2, PHY_TEST_CTRL_REG, 0x0); sleep(1); writeReg(&nf2, PHY_TEST_PATTERN_REG, PHY_TEST_PATTERN_ENABLE_MASK); // Start the test writeReg(&nf2, PHY_TEST_CTRL_REG, PHY_TEST_CTRL_REPEAT); } // phyResetContinuous1,1Top "selftest_phy.c" 160L, 4050C1,1Top[?12l[?25hP+q6b33\[?25l[?12l[?25hP+q6b34\P+q6b35\P+q6b36\P+q6b37\P+q6b38\P+q6b39\P+q6b3b\P+q4631\P+q4632\P+q2531\P+q2638\P+q6b62\P+q6b49\P+q6b44\P+q6b68\P+q4037\P+q6b50\P+q6b4e\P+q4b31\P+q4b33\P+q4b34\P+q4b35\P+q6b42\[?25l/[?12l[?25hK[?25l[?12l[?25hi[?25l[?12l[?25hr[?25l[?12l[?25ha[?25l[?12l[?25hn[?25l[?12l[?25h [?25lvoid phyStopContinuous(void) { // Stop the test (and wait for the test to stop) writeReg(&nf2, PHY_TEST_CTRL_REG, 0x00000000); } // phyStopContinuous /* * Get the result of the test * * Return -- boolean indicating success */ int phyGetResult(void) { unsigned int val; unsigned int port_status; unsigned int good_pkts; unsigned int bad_pkts; int i; int good = 1; // Read the individual port registers for (i = 0; i < NUM_PORTS; i++) { // Start with the status register readReg(&nf2, PHY_TEST_PHY_0_RX_STATUS_REG + i * PHY_TEST_PHY_GROUP_INST_OFFSET, &port_status); if ((port_status & 0x100) == 0) { //Kiran printw("phyGetResult: port status bad"); good = 0; } // Read the number of good/bad packets readReg(&nf2, PHY_TEST_PHY_0_RX_GOOD_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INST_OFFSET, &good_pkts); readReg(&nf2, PHY_TEST_PHY_0_RX_ERR_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INST_OFFSET, &bad_pkts); // Update the good flag if (bad_pkts != 0) { printw("phyGetResult: found bad packets"); good = 0; } } return good; } // phyGetResult143,4-11 Bot[?12l[?25h[?25l2,11 [?12l[?25h[?25l1[?12l[?25h[?25l0[?12l[?25h[?25l39[?12l[?25h[?25l8[?12l[?25h[?25l7,0-1[?12l[?25h[?25l6,11 [?12l[?25h[?25l5,0-1[?12l[?25h[?25l4,8 [?12l[?25h[?25l3,0-1[?12l[?25h[?25l2,11 [?12l[?25h[?25l1[?12l[?25h[?25l0[?12l[?25h[?25l29[?12l[?25h[?25l8[?12l[?25h[?25l7,3 [?12l[?25h[?25l6,11[?12l[?25h[?25l5,2 [?12l[?25h[?25l4,11[?12l[?25h[?25l3,2 [?12l[?25h[?25l2,0-1[?12l[?25h[?25l1,11 [?12l[?25h[?25l()0[?12l[?25h[?25l()19[?12l[?25h[?25l8[?12l[?25h[?25l */117,399%[?12l[?25h[?25l * Stop the interface116,1198%[?12l[?25h[?25l/*115,297%[?12l[?25h[?25l114,0-196%[?12l[?25h[?25l} // phyShowStatusContinuous113,1195%[?12l[?25h[?25l return good;112,1194%[?12l[?25h[?25l111,0-194%[?12l[?25h[?25l move(y + 1 + NUM_PORTS, x);110,1193%[?12l[?25h[?25l printw("PHY test: %s", good ? "pass" : "fail");109,1192%[?12l[?25h[?25l move(y, x);108,1191%[?12l[?25h[?25l // Print overall success/failure107,1190%[?12l[?25h[?25l106,0-189%[?12l[?25h[?25l }105,388%[?12l[?25h[?25l good = 0;104,1188%[?12l[?25h[?25l if (bad_pkts != 0)103,1187%[?12l[?25h[?25l // Update the good flag102,1186%[?12l[?25h[?25l101,0-185%[?12l[?25h[?25l }*/100,784%[?12l[?25h[?25l1,0-1[?12l[?25h[?25l2,11 [?12l[?25h[?25l3[?12l[?25h[?25l4[?12l[?25h[?25l5,3 [?12l[?25h[?25l6,0-1[?12l[?25h[?25l7,11 [?12l[?25h[?25l8[?12l[?25h[?25l9[?12l[?25h[?25l10[?12l[?25h[?25l1,0-1[?12l[?25h[?25l0,11 [?12l[?25h[?25l09[?12l[?25h[?25l8[?12l[?25h[?25l7[?12l[?25h[?25l6,0-1[?12l[?25h[?25l5,3 [?12l[?25h[?25l4,11[?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l1,0-1[?12l[?25h[?25l0,7 [?12l[?25h[?25l prev_good_pkts[i] = good_pkts;99,1183%[?12l[?25h[?25l prev_bad_pkts[i] = bad_pkts;98,1182%[?12l[?25h[?25l // Update the counters97,1182%[?12l[?25h[?25l96,0-181%[?12l[?25h[?25l }95,780%[?12l[?25h[?25l writeReg(&nf2, PHY_TEST_PHY_0_RX_CTRL_REG + i * PHY_TEST_PHY_GROUP_INST_OFFSET, 0x3);94,1179%[?12l[?25h[?25l if (bad_pkts == prev_bad_pkts[i] && good_pkts != prev_good_pkts[i]) {93,1178%[?12l[?25h[?25l // packets have remained the same92,1177%[?12l[?25h[?25l // Only reset if the number of good packets has incremented but the bad91,1176%[?12l[?25h[?25l /*if ((port_status & 0x1100) == 0x1100) {90,1176%[?12l[?25h[?25l // Verify if we should reset the counters()89,1175%[?12l[?25h[?25l()90[?12l[?25h[?25l()1[?12l[?25h[?25l2[?12l[?25h[?25l3[?12l[?25h[?25l4[?12l[?25h[?25l{}5,7 [?12l[?25h[?25l{}6,0-1[?12l[?25h[?25l7,11 [?12l[?25h[?25l8[?12l[?25h[?25l9[?12l[?25h[?25l100,7[?12l[?25h[?25l1,0-1[?12l[?25h[?25l2,11 [?12l[?25h[?25l3[?12l[?25h[?25l4[?12l[?25h[?25l5,3 [?12l[?25h[?25l6,0-1[?12l[?25h[?25l7,11 [?12l[?25h[?25l8[?12l[?25h[?25l9[?12l[?25h[?25l10[?12l[?25h[?25l1,0-1[?12l[?25h[?25l2,11 [?12l[?25h[?25l3[?12l[?25h[?25l4,0-1[?12l[?25h[?25l5,2 [?12l[?25h[?25l6,11[?12l[?25h[?25l7,3 [?12l[?25h[?25l8,11[?12l[?25h[?25l9[?12l[?25h[?25l()20[?12l[?25h[?25l()1[?12l[?25h[?25l2,0-1[?12l[?25h[?25l3,2 [?12l[?25h[?25l4,11[?12l[?25h[?25l5,2 [?12l[?25h[?25l6,11[?12l[?25h[?25l7,3 [?12l[?25h[?25l8,11[?12l[?25h[?25l9[?12l[?25h[?25l30[?12l[?25h[?25l1[?12l[?25h[?25l  unsigned int bad_pkts;132,1176%[?12l[?25h[?25l 133,0-176%[?12l[?25h[?25l  int i;134,877%[?12l[?25h[?25l 135,0-178%[?12l[?25h[?25l  int good = 1;136,1179%[?12l[?25h[?25l 137,0-180%[?12l[?25h[?25l  // Read the individual port registers138,1181%[?12l[?25h[?25l  for (i = 0; i < NUM_PORTS; i++) {139,1182%[?12l[?25h[?25l  // Start with the status register140,1182%[?12l[?25h[?25l  readReg(&nf2, PHY_TEST_PHY_0_RX_STATUS_REG + i * PHY_TEST_PHY_GROUP_INST_OFFSET, &port_status);141,1183%[?12l[?25h[?25l  if ((port_status & 0x100) == 0) {142,1184%[?12l[?25h[?25l  //Kiran143,4-11 85%[?12l[?25h[?25l  printw("phyGetResult: port status bad");144,4-11 86%[?12l[?25h[?25l  good = 0;145,1187%[?12l[?25h[?25l { }146,588%[?12l[?25h[?25l {}147,0-188%[?12l[?25h[?25l  // Read the number of good/bad packets148,1189%[?12l[?25h[?25l  readReg(&nf2, PHY_TEST_PHY_0_RX_GOOD_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INST_OFFSET, &good_pkts);149,1190%[?12l[?25h[?25l  readReg(&nf2, PHY_TEST_PHY_0_RX_ERR_PKT_CNT_REG + i * PHY_TEST_PHY_GROUP_INST_OFFSET, &bad_pkts);150,1191%[?12l[?25h[?25l 151,0-192%[?12l[?25h[?25l  // Update the good flag152,1193%[?12l[?25h[?25l  if (bad_pkts != 0) {153,1194%[?12l[?25h[?25l  printw("phyGetResult: found bad packets");154,4-11 94%[?12l[?25h[?25l  good = 0;155,1195%[?12l[?25h[?25l { }156,596%[?12l[?25h[?25l {{} }157,397%[?12l[?25h[?25l {}158,0-198%[?12l[?25h[?25l  return good;159,1199%[?12l[?25h[?25l } // phyGetResult160,11Bot[?12l[?25h[?25l59[?12l[?25h[?25l8,0-1[?12l[?25h[?25l{}7,3 [?12l[?25h[?25l{{} }6,5[?12l[?25h[?25l{}5,11[?12l[?25h[?25l4,4-11[?12l[?25h[?25l3,11 [?12l[?25h[?25l2[?12l[?25h[?25l1,0-1[?12l[?25h[?25l0,11 [?12l[?25h[?25l49[?12l[?25h[?25l8[?12l[?25h[?25l7,0-1[?12l[?25h[?25l{}6,5 [?12l[?25h[?25l{}5,11[?12l[?25h[?25l4,4-11[?12l[?25h[?25l5-12[?12l[?25h[?25l6-13[?12l[?25h[?25l7-14[?12l[?25h[?25ltf[?12l[?25h[?25l5,14 [?12l[?25h[?25l{}6,5 [?12l[?25h[?25l{}7,0-1[?12l[?25h[?25l8,14 [?12l[?25h[?25l9[?12l[?25h[?25l50[?12l[?25h[?25l1,0-1[?12l[?25h[?25l2,14 [?12l[?25h[?25l3[?12l[?25h[?25l4,7-14[?12l[?25h[?25ltf[?12l[?25h[?25l:[?12l[?25hw[?25l[?12l[?25hq[?25l[?12l[?25h [?25l"selftest_phy.c" 160L, 4050C written [?1l>[?12l[?25h[?1049l]0;netfpga@node1-1: ~/netfpga/projects/selftest/swnetfpga@node1-1:~/netfpga/projects/selftest/sw$ make /bin/nf_register_gen.pl --project selftest make: /bin/nf_register_gen.pl: Command not found make: *** [registers] Error 127 ]0;netfpga@node1-1: ~/netfpga/projects/selftest/swnetfpga@node1-1:~/netfpga/projects/selftest/sw$ cd - /home/netfpga/netfpga ]0;netfpga@node1-1: ~/netfpganetfpga@node1-1:~/netfpga$ make echo /home/netfpga/netfpga/lib/Perl5: /home/netfpga/netfpga/lib/Perl5: if [ -f "lib/Makefile" ] ; then \ make -C lib ; \ fi make[1]: Entering directory `/home/netfpga/netfpga/lib' make -C C make[2]: Entering directory `/home/netfpga/netfpga/lib/C' make -C kernel make[3]: Entering directory `/home/netfpga/netfpga/lib/C/kernel' make -C /lib/modules/2.6.31-19-generic/build M=/home/netfpga/netfpga/lib/C/kernel LDDINC=/home/netfpga/netfpga/lib/C/kernel/../include modules make[4]: Entering directory `/usr/src/linux-headers-2.6.31-19-generic' Building modules, stage 2. MODPOST 1 modules make[4]: Leaving directory `/usr/src/linux-headers-2.6.31-19-generic' make[3]: Leaving directory `/home/netfpga/netfpga/lib/C/kernel' make -C download make[3]: Entering directory `/home/netfpga/netfpga/lib/C/download' make -C ../common make[4]: Entering directory `/home/netfpga/netfpga/lib/C/common' make[4]: Nothing to be done for `all'. make[4]: Leaving directory `/home/netfpga/netfpga/lib/C/common' make[3]: Leaving directory `/home/netfpga/netfpga/lib/C/download' make -C reg_access make[3]: Entering directory `/home/netfpga/netfpga/lib/C/reg_access' make -C ../common make[4]: Entering directory `/home/netfpga/netfpga/lib/C/common' make[4]: Nothing to be done for `all'. make[4]: Leaving directory `/home/netfpga/netfpga/lib/C/common' make[3]: Leaving directory `/home/netfpga/netfpga/lib/C/reg_access' make -C tools make[3]: Entering directory `/home/netfpga/netfpga/lib/C/tools' make -C nf_info make[4]: Entering directory `/home/netfpga/netfpga/lib/C/tools/nf_info' make -C ../../common make[5]: Entering directory `/home/netfpga/netfpga/lib/C/common' make[5]: Nothing to be done for `all'. make[5]: Leaving directory `/home/netfpga/netfpga/lib/C/common' make[4]: Leaving directory `/home/netfpga/netfpga/lib/C/tools/nf_info' make[3]: Leaving directory `/home/netfpga/netfpga/lib/C/tools' make[2]: Leaving directory `/home/netfpga/netfpga/lib/C' make -C scripts make[2]: Entering directory `/home/netfpga/netfpga/lib/scripts' make -C cpci_reprogram make[3]: Entering directory `/home/netfpga/netfpga/lib/scripts/cpci_reprogram' make[3]: Nothing to be done for `all'. make[3]: Leaving directory `/home/netfpga/netfpga/lib/scripts/cpci_reprogram' make -C cpci_config_reg_access make[3]: Entering directory `/home/netfpga/netfpga/lib/scripts/cpci_config_reg_access' make[3]: Nothing to be done for `all'. make[3]: Leaving directory `/home/netfpga/netfpga/lib/scripts/cpci_config_reg_access' make[2]: Leaving directory `/home/netfpga/netfpga/lib/scripts' make[1]: Leaving directory `/home/netfpga/netfpga/lib' echo /home/netfpga/netfpga/lib/Perl5: /home/netfpga/netfpga/lib/Perl5: if [ -f "bitfiles/Makefile" ] ; then \ make -C bitfiles ; \ fi make[1]: Entering directory `/home/netfpga/netfpga/bitfiles' make[1]: Nothing to be done for `all'. make[1]: Leaving directory `/home/netfpga/netfpga/bitfiles' echo /home/netfpga/netfpga/lib/Perl5: /home/netfpga/netfpga/lib/Perl5: if [ -f "projects/Makefile" ] ; then \ make -C projects ; \ fi make[1]: Entering directory `/home/netfpga/netfpga/projects' make -C reference_nic make[2]: Entering directory `/home/netfpga/netfpga/projects/reference_nic' make -C sw make[3]: Entering directory `/home/netfpga/netfpga/projects/reference_nic/sw' /home/netfpga/netfpga/bin/nf_register_gen.pl --project reference_nic NetFPGA environment: Root dir: /home/netfpga/netfpga Project name: reference_nic Project dir: /home/netfpga/netfpga/projects/reference_nic Work dir: /tmp/netfpga Processing /home/netfpga/netfpga/lib/verilog/core/common/xml/global.xml... Processing /home/netfpga/netfpga/lib/verilog/core/common/xml/nf_defines.xml... Processing /home/netfpga/netfpga/projects/reference_nic/include/project.xml... Project: 'Reference NIC' (reference_nic) Description: Reference NIC Version: 1.1.0 Device ID: 1 Processing /home/netfpga/netfpga/lib/verilog/core/io_queues/cpu_dma_queue/xml/cpu_dma_queue.xml... Processing /home/netfpga/netfpga/lib/verilog/core/io_queues/ethernet_queue/xml/ethernet_mac.xml... WARNING: No module specific XML found for module 'contrib/ucsd/gig_eth_mac' Processing /home/netfpga/netfpga/lib/verilog/core/input_arbiter/rr_input_arbiter/xml/rr_input_arbiter.xml... WARNING: No module specific XML found for module 'core/nf2/generic_top' WARNING: No module specific XML found for module 'core/nf2/reference_core' WARNING: No module specific XML found for module 'core/output_port_lookup/nic' Processing /home/netfpga/netfpga/lib/verilog/core/output_queues/sram_rr_output_queues/xml/sram_rr_output_queues.xml... WARNING: No module specific XML found for module 'core/sram_arbiter/sram_weighted_rr' WARNING: No module specific XML found for module 'core/user_data_path/reference_user_data_path' Processing /home/netfpga/netfpga/lib/verilog/core/io/mdio/xml/mdio.xml... WARNING: No module specific XML found for module 'core/cpci_bus' Processing /home/netfpga/netfpga/lib/verilog/core/dma/xml/dma.xml... WARNING: No module specific XML found for module 'core/user_data_path/udp_reg_master' WARNING: No module specific XML found for module 'core/io_queues/add_rm_hdr' Processing /home/netfpga/netfpga/lib/verilog/core/strip_headers/keep_length/xml/strip_headers.xml... Processing /home/netfpga/netfpga/lib/verilog/core/utils/xml/device_id_reg.xml... WARNING: No module specific XML found for module 'core/utils/generic_regs' make[3]: Leaving directory `/home/netfpga/netfpga/projects/reference_nic/sw' make[2]: Leaving directory `/home/netfpga/netfpga/projects/reference_nic' make -C reference_router make[2]: Entering directory `/home/netfpga/netfpga/projects/reference_router' make -C sw make[3]: Entering directory `/home/netfpga/netfpga/projects/reference_router/sw' /home/netfpga/netfpga/bin/nf_register_gen.pl --project reference_router NetFPGA environment: Root dir: /home/netfpga/netfpga Project name: reference_router Project dir: /home/netfpga/netfpga/projects/reference_router Work dir: /tmp/netfpga Processing /home/netfpga/netfpga/lib/verilog/core/common/xml/global.xml... Processing /home/netfpga/netfpga/lib/verilog/core/common/xml/nf_defines.xml... Processing /home/netfpga/netfpga/projects/reference_router/include/project.xml... Project: 'Reference router' (reference_router) Description: Reference IPv4 router Version: 1.0.0 Device ID: 2 Processing /home/netfpga/netfpga/lib/verilog/core/io_queues/cpu_dma_queue/xml/cpu_dma_queue.xml... Processing /home/netfpga/netfpga/lib/verilog/core/io_queues/ethernet_queue/xml/ethernet_mac.xml... WARNING: No module specific XML found for module 'contrib/ucsd/gig_eth_mac' Processing /home/netfpga/netfpga/lib/verilog/core/input_arbiter/rr_input_arbiter/xml/rr_input_arbiter.xml... WARNING: No module specific XML found for module 'core/nf2/generic_top' WARNING: No module specific XML found for module 'core/nf2/reference_core' Processing /home/netfpga/netfpga/lib/verilog/core/output_port_lookup/cam_router/xml/cam_router.xml... Processing /home/netfpga/netfpga/lib/verilog/core/output_queues/sram_rr_output_queues/xml/sram_rr_output_queues.xml... WARNING: No module specific XML found for module 'core/sram_arbiter/sram_weighted_rr' WARNING: No module specific XML found for module 'core/user_data_path/reference_user_data_path' Processing /home/netfpga/netfpga/lib/verilog/core/io/mdio/xml/mdio.xml... WARNING: No module specific XML found for module 'core/cpci_bus' Processing /home/netfpga/netfpga/lib/verilog/core/dma/xml/dma.xml... WARNING: No module specific XML found for module 'core/user_data_path/udp_reg_master' WARNING: No module specific XML found for module 'core/io_queues/add_rm_hdr' Processing /home/netfpga/netfpga/lib/verilog/core/strip_headers/keep_length/xml/strip_headers.xml... Processing /home/netfpga/netfpga/lib/verilog/core/utils/xml/device_id_reg.xml... WARNING: No module specific XML found for module 'core/utils/generic_regs' make[3]: Leaving directory `/home/netfpga/netfpga/projects/reference_router/sw' make[2]: Leaving directory `/home/netfpga/netfpga/projects/reference_router' make -C reference_switch make[2]: Entering directory `/home/netfpga/netfpga/projects/reference_switch' make -C sw make[3]: Entering directory `/home/netfpga/netfpga/projects/reference_switch/sw' /home/netfpga/netfpga/bin/nf_register_gen.pl --project reference_switch NetFPGA environment: Root dir: /home/netfpga/netfpga Project name: reference_switch Project dir: /home/netfpga/netfpga/projects/reference_switch Work dir: /tmp/netfpga Processing /home/netfpga/netfpga/lib/verilog/core/common/xml/global.xml... Processing /home/netfpga/netfpga/lib/verilog/core/common/xml/nf_defines.xml... Processing /home/netfpga/netfpga/projects/reference_switch/include/project.xml... Project: 'Reference Switch' (reference_switch) Description: Reference Switch Version: 1.0.0 Device ID: 3 Processing /home/netfpga/netfpga/lib/verilog/core/io_queues/cpu_dma_queue/xml/cpu_dma_queue.xml... Processing /home/netfpga/netfpga/lib/verilog/core/io_queues/ethernet_queue/xml/ethernet_mac.xml... WARNING: No module specific XML found for module 'contrib/ucsd/gig_eth_mac' Processing /home/netfpga/netfpga/lib/verilog/core/input_arbiter/rr_input_arbiter/xml/rr_input_arbiter.xml... WARNING: No module specific XML found for module 'core/nf2/generic_top' WARNING: No module specific XML found for module 'core/nf2/reference_core' Processing /home/netfpga/netfpga/lib/verilog/core/output_port_lookup/learning_cam_switch/xml/learning_cam_switch.xml... Processing /home/netfpga/netfpga/lib/verilog/core/output_queues/sram_rr_output_queues/xml/sram_rr_output_queues.xml... WARNING: No module specific XML found for module 'core/sram_arbiter/sram_weighted_rr' WARNING: No module specific XML found for module 'core/user_data_path/reference_user_data_path' WARNING: No module specific XML found for module 'core/user_data_path/udp_reg_master' Processing /home/netfpga/netfpga/lib/verilog/core/io/mdio/xml/mdio.xml... WARNING: No module specific XML found for module 'core/cpci_bus' Processing /home/netfpga/netfpga/lib/verilog/core/dma/xml/dma.xml... WARNING: No module specific XML found for module 'core/io_queues/add_rm_hdr' Processing /home/netfpga/netfpga/lib/verilog/core/strip_headers/keep_length/xml/strip_headers.xml... Processing /home/netfpga/netfpga/lib/verilog/core/utils/xml/device_id_reg.xml... make[3]: Leaving directory `/home/netfpga/netfpga/projects/reference_switch/sw' make[2]: Leaving directory `/home/netfpga/netfpga/projects/reference_switch' make -C router_buffer_sizing make[2]: Entering directory `/home/netfpga/netfpga/projects/router_buffer_sizing' make -C sw make[3]: Entering directory `/home/netfpga/netfpga/projects/router_buffer_sizing/sw' make[3]: Nothing to be done for `all'. make[3]: Leaving directory `/home/netfpga/netfpga/projects/router_buffer_sizing/sw' make[2]: Leaving directory `/home/netfpga/netfpga/projects/router_buffer_sizing' make -C router_kit make[2]: Entering directory `/home/netfpga/netfpga/projects/router_kit' make -C sw make[3]: Entering directory `/home/netfpga/netfpga/projects/router_kit/sw' /home/netfpga/netfpga/bin/nf_register_gen.pl --project reference_router NetFPGA environment: Root dir: /home/netfpga/netfpga Project name: reference_router Project dir: /home/netfpga/netfpga/projects/reference_router Work dir: /tmp/netfpga Processing /home/netfpga/netfpga/lib/verilog/core/common/xml/global.xml... Processing /home/netfpga/netfpga/lib/verilog/core/common/xml/nf_defines.xml... Processing /home/netfpga/netfpga/projects/reference_router/include/project.xml... Project: 'Reference router' (reference_router) Description: Reference IPv4 router Version: 1.0.0 Device ID: 2 Processing /home/netfpga/netfpga/lib/verilog/core/io_queues/cpu_dma_queue/xml/cpu_dma_queue.xml... Processing /home/netfpga/netfpga/lib/verilog/core/io_queues/ethernet_queue/xml/ethernet_mac.xml... WARNING: No module specific XML found for module 'contrib/ucsd/gig_eth_mac' Processing /home/netfpga/netfpga/lib/verilog/core/input_arbiter/rr_input_arbiter/xml/rr_input_arbiter.xml... WARNING: No module specific XML found for module 'core/nf2/generic_top' WARNING: No module specific XML found for module 'core/nf2/reference_core' Processing /home/netfpga/netfpga/lib/verilog/core/output_port_lookup/cam_router/xml/cam_router.xml... Processing /home/netfpga/netfpga/lib/verilog/core/output_queues/sram_rr_output_queues/xml/sram_rr_output_queues.xml... WARNING: No module specific XML found for module 'core/sram_arbiter/sram_weighted_rr' WARNING: No module specific XML found for module 'core/user_data_path/reference_user_data_path' Processing /home/netfpga/netfpga/lib/verilog/core/io/mdio/xml/mdio.xml... WARNING: No module specific XML found for module 'core/cpci_bus' Processing /home/netfpga/netfpga/lib/verilog/core/dma/xml/dma.xml... WARNING: No module specific XML found for module 'core/user_data_path/udp_reg_master' WARNING: No module specific XML found for module 'core/io_queues/add_rm_hdr' Processing /home/netfpga/netfpga/lib/verilog/core/strip_headers/keep_length/xml/strip_headers.xml... Processing /home/netfpga/netfpga/lib/verilog/core/utils/xml/device_id_reg.xml... WARNING: No module specific XML found for module 'core/utils/generic_regs' ln -f -s ../../reference_router/lib/C/reg_defines_reference_router.h reg_defines.h make[3]: Leaving directory `/home/netfpga/netfpga/projects/router_kit/sw' make[2]: Leaving directory `/home/netfpga/netfpga/projects/router_kit' make -C scone make[2]: Entering directory `/home/netfpga/netfpga/projects/scone' make -C sw make[3]: Entering directory `/home/netfpga/netfpga/projects/scone/sw' /home/netfpga/netfpga/bin/nf_register_gen.pl --project reference_router NetFPGA environment: Root dir: /home/netfpga/netfpga Project name: reference_router Project dir: /home/netfpga/netfpga/projects/reference_router Work dir: /tmp/netfpga Processing /home/netfpga/netfpga/lib/verilog/core/common/xml/global.xml... Processing /home/netfpga/netfpga/lib/verilog/core/common/xml/nf_defines.xml... Processing /home/netfpga/netfpga/projects/reference_router/include/project.xml... Project: 'Reference router' (reference_router) Description: Reference IPv4 router Version: 1.0.0 Device ID: 2 Processing /home/netfpga/netfpga/lib/verilog/core/io_queues/cpu_dma_queue/xml/cpu_dma_queue.xml... Processing /home/netfpga/netfpga/lib/verilog/core/io_queues/ethernet_queue/xml/ethernet_mac.xml... WARNING: No module specific XML found for module 'contrib/ucsd/gig_eth_mac' Processing /home/netfpga/netfpga/lib/verilog/core/input_arbiter/rr_input_arbiter/xml/rr_input_arbiter.xml... WARNING: No module specific XML found for module 'core/nf2/generic_top' WARNING: No module specific XML found for module 'core/nf2/reference_core' Processing /home/netfpga/netfpga/lib/verilog/core/output_port_lookup/cam_router/xml/cam_router.xml... Processing /home/netfpga/netfpga/lib/verilog/core/output_queues/sram_rr_output_queues/xml/sram_rr_output_queues.xml... WARNING: No module specific XML found for module 'core/sram_arbiter/sram_weighted_rr' WARNING: No module specific XML found for module 'core/user_data_path/reference_user_data_path' Processing /home/netfpga/netfpga/lib/verilog/core/io/mdio/xml/mdio.xml... WARNING: No module specific XML found for module 'core/cpci_bus' Processing /home/netfpga/netfpga/lib/verilog/core/dma/xml/dma.xml... WARNING: No module specific XML found for module 'core/user_data_path/udp_reg_master' WARNING: No module specific XML found for module 'core/io_queues/add_rm_hdr' Processing /home/netfpga/netfpga/lib/verilog/core/strip_headers/keep_length/xml/strip_headers.xml... Processing /home/netfpga/netfpga/lib/verilog/core/utils/xml/device_id_reg.xml... WARNING: No module specific XML found for module 'core/utils/generic_regs' ln -f -s /home/netfpga/netfpga/projects/reference_router/lib/C/reg_defines_reference_router.h reg_defines.h make[3]: Leaving directory `/home/netfpga/netfpga/projects/scone/sw' make[2]: Leaving directory `/home/netfpga/netfpga/projects/scone' make -C selftest make[2]: Entering directory `/home/netfpga/netfpga/projects/selftest' make -C sw make[3]: Entering directory `/home/netfpga/netfpga/projects/selftest/sw' /home/netfpga/netfpga/bin/nf_register_gen.pl --project selftest NetFPGA environment: Root dir: /home/netfpga/netfpga Project name: selftest Project dir: /home/netfpga/netfpga/projects/selftest Work dir: /tmp/netfpga Processing /home/netfpga/netfpga/lib/verilog/core/common/xml/global.xml... Processing /home/netfpga/netfpga/lib/verilog/core/common/xml/nf_defines.xml... Processing /home/netfpga/netfpga/projects/selftest/include/project.xml... Project: 'Selftest' (selftest) Description: NetFPGA selftest -- exercises all major subsystems of the board Version: 1.1.0 Device ID: 5 WARNING: No module specific XML found for module 'core/nf2/reference_core' Processing /home/netfpga/netfpga/lib/verilog/core/io/mdio/xml/mdio.xml... WARNING: No module specific XML found for module 'core/cpci_bus' Processing /home/netfpga/netfpga/lib/verilog/core/dma/xml/dma.xml... WARNING: No module specific XML found for module 'core/ddr2_controller' Processing /home/netfpga/netfpga/lib/verilog/core/utils/xml/device_id_reg.xml... Processing /home/netfpga/netfpga/projects/selftest/include/clock_test.xml... Processing /home/netfpga/netfpga/projects/selftest/include/dram_test.xml... Processing /home/netfpga/netfpga/projects/selftest/include/phy_test.xml... Processing /home/netfpga/netfpga/projects/selftest/include/reg_file.xml... Processing /home/netfpga/netfpga/projects/selftest/include/reg_reflect.xml... Processing /home/netfpga/netfpga/projects/selftest/include/serial_test.xml... Processing /home/netfpga/netfpga/projects/selftest/include/sram_msb.xml... Processing /home/netfpga/netfpga/projects/selftest/include/sram_test.xml... /home/netfpga/netfpga/bin/nf_register_gen.pl --project cpci NetFPGA environment: Root dir: /home/netfpga/netfpga Project name: cpci Project dir: /home/netfpga/netfpga/projects/cpci Work dir: /tmp/netfpga Processing /home/netfpga/netfpga/lib/verilog/core/common/xml/global.xml... Processing /home/netfpga/netfpga/lib/verilog/core/common/xml/nf_defines.xml... Processing /home/netfpga/netfpga/projects/cpci/include/project.xml... Project: 'CPCI' (cpci) Description: NetFPGA PCI interface Version: 4.1.0 Device ID: 0 Processing /home/netfpga/netfpga/projects/cpci/include/cpci_regs.xml... gcc -g -c -o selftest_phy.o selftest_phy.c gcc -lncurses selftest.o selftest_dram.o selftest_sram.o selftest_serial.o selftest_phy.o selftest_mdio.o selftest_reg.o selftest_clk.o selftest_dma.o or_ip.o or_utils.o /home/netfpga/netfpga/lib/C/common/nf2util.o /home/netfpga/netfpga/lib/C/common/nf2util_proxy_common.o -o selftest make[3]: Leaving directory `/home/netfpga/netfpga/projects/selftest/sw' make[2]: Leaving directory `/home/netfpga/netfpga/projects/selftest' make[1]: Leaving directory `/home/netfpga/netfpga/projects' ]0;netfpga@node1-1: ~/netfpganetfpga@node1-1:~/netfpga$ cd - /home/netfpga/netfpga/projects/selftest/sw ]0;netfpga@node1-1: ~/netfpga/projects/selftest/swnetfpga@node1-1:~/netfpga/projects/selftest/sw$ cd -makecd -makesudo selectftest,../selftest -n Found net device: nf2c0 CPCI Information ---------------- Version: 4 (rev 1) Device (Virtex) Information --------------------------- Project directory: selftest Project name: Selftest Project description: NetFPGA selftest -- exercises all major subsystems of the board Device ID: 5 Version: 1.1.0 Built against CPCI version: 4 (rev 1) NetFPGA selftest 1.00 alpha Running..... phyGetResult: port status badphyGetResult: found bad packetsphyGetResult: port status badphyGetResult: found bad packetsphyGetResult: port status badphyGetResult: found bad packetsphyGetResult: port status badphyGetResult: found bad packetsFAILED. Failing tests: PHY interface, DMA interface ]0;netfpga@node1-1: ~/netfpga/projects/selftest/swnetfpga@node1-1:~/netfpga/projects/selftest/sw$ sudo bashsu - ]0;root@node1-1.sb9.orbit-lab.org: ~root@node1-1:~# cd /hoexitlsshutdown -r nowupdate-grub~netfpga/projnetfpga/projects/selftest/sw/ bad_pkt_dump selftest root@node1-1:~# ~netfpga/netfpga/projects/selftest/sw/selftest -mn Found net device: nf2c0 CPCI Information ---------------- Version: 4 (rev 1) Device (Virtex) Information --------------------------- Project directory: selftest Project name: Selftest Project description: NetFPGA selftest -- exercises all major subsystems of the board Device ID: 5 Version: 1.1.0 Built against CPCI version: 4 (rev 1) NetFPGA selftest 1.00 alpha Running..... phyGetResult: port status badphyGetResult: found bad packetsphyGetResult: port status badphyGetResult: found bad packetsphyGetResult: port status badphyGetResult: found bad packetsphyGetResult: port status badphyGetResult: found bad packetsFAILED. Failing tests: PHY interface ]0;root@node1-1.sb9.orbit-lab.org: ~root@node1-1:~# ls omf-common-5.2_ubuntu2_all.deb ]0;root@node1-1.sb9.orbit-lab.org: ~root@node1-1:~# ls -al total 188 drwx------ 6 root root 4096 2011-03-09 20:36 . drwxr-xr-x 21 root root 4096 2010-10-22 03:51 .. drwx------ 2 root root 4096 2010-01-29 02:36 .aptitude -rw------- 1 root root 751 2011-03-10 14:50 .bash_history -rw-r--r-- 1 root root 2227 2009-04-27 09:56 .bashrc drwxr-xr-x 2 root root 4096 2010-02-01 05:12 .cache drwxr-xr-x 2 root root 4096 2010-01-29 02:36 .debtags -rw-r--r-- 1 root root 140614 2011-01-19 04:26 omf-common-5.2_ubuntu2_all.deb -rw-r--r-- 1 root root 140 2007-11-19 17:57 .profile -rw------- 1 root root 6120 2011-03-09 20:36 .viminfo drwx------ 2 root root 4096 2010-02-01 05:44 .w3m ]0;root@node1-1.sb9.orbit-lab.org: ~root@node1-1:~# exit logout ]0;netfpga@node1-1: ~/netfpga/projects/selftest/swnetfpga@node1-1:~/netfpga/projects/selftest/sw$ vi selftest.c_phy.ct.c [?1049h[?1h=[?12;25h[?12l[?25h[?25l"selftest.c" 512L, 10370C[>c/* **************************************************************************** * vim:set shiftwidth=2 softtabstop=2 expandtab: * $Id: selftest.c 6010 2010-03-14 08:24:50Z grg $ * * Module: selftest.c * Project: NetFPGA 2.1 * Description: Interface with the self-test modules on the NetFPGA * to help diagnose problems. * * Change history: * */ #include  #include  #include  #include  #include  #include  #include  #include  #include  #include  #include "../lib/C/reg_defines_selftest.h" #include "../../cpci/lib/C/reg_defines_cpci.h" #include "../../../lib/C/common/nf2util.h" #include  #include "selftest.h" #include "selftest_dram.h" #include "selftest_sram.h" #include "selftest_serial.h" #include "selftest_phy.h" #include "selftest_mdio.h" #include "selftest_reg.h" #include "selftest_clk.h" #include "selftest_dma.h" #define PATHLEN 801,1Top[?12l[?25hP+q436f\P+q6b75\P+q6b64\P+q6b72\P+q6b6c\P+q2332\P+q2334\P+q2569\P+q2a37\P+q6b31\P+q6b32\[?25l/* **************************************************************************** * vim:set shiftwidth=2 softtabstop=2 expandtab: * $Id: selftest.c 6010 2010-03-14 08:24:50Z grg $ * * Module: selftest.c * Project: NetFPGA 2.1 * Description: Interface with the self-test modules on the NetFPGA * to help diagnose problems. * * Change history: * */ #include  #include  #include  #include  #include  #include  #include  #include  #include  #include  #include "../lib/C/reg_defines_selftest.h" #include "../../cpci/lib/C/reg_defines_cpci.h" #include "../../../lib/C/common/nf2util.h" #include  #include "selftest.h" #include "selftest_dram.h" #include "selftest_sram.h" #include "selftest_serial.h" #include "selftest_phy.h" #include "selftest_mdio.h" #include "selftest_reg.h" #include "selftest_clk.h" #include "selftest_dma.h" #define PATHLEN 801,1Top "selftest.c" 512L, 10370C1,1Top[?12l[?25hP+q6b33\[?25l[?12l[?25hP+q6b34\P+q6b35\P+q6b36\P+q6b37\P+q6b38\P+q6b39\P+q6b3b\P+q4631\P+q4632\P+q2531\P+q2638\P+q6b62\P+q6b49\P+q6b44\P+q6b68\P+q4037\P+q6b50\P+q6b4e\P+q4b31\P+q4b33\P+q4b34\P+q4b35\P+q6b42\[?25l:[?12l[?25h$[?25l[?12l[?25h [?25l// verbose = 1; // break; // case 'l': /* log file */ // log_file_name = optarg; // break; case 'i': /* interface name */ nf2.device_name = optarg; break; case 'n': /* without SATA test */ no_sata_flg = 1; break; case '?': if (isprint (optopt)) fprintf (stderr, "Unknown option `-%c'.\n", optopt); else fprintf (stderr, "Unknown option character `\\x%x'.\n", optopt); default: usage(argv[0]); exit(1); } // if (verbose) { // printf ("logfile = %s. bin file = %s\n", log_file_name, bin_file_name); // } } /* * Describe usage of this program. */ void usage (char *prog) { printf("Usage: %s [filename.bin | filename.bit]\n", prog); printf("\nOptions: -l (default is stdout).\n"); printf(" -i : interface name.\n"); printf(" -v : be verbose.\n"); printf(" -c : run continuously\n"); printf(" -s : short test mode\n"); printf(" -n : disable SATA testing\n"); }512,0-1Bot[?12l[?25h[?25l1[?12l[?25h[?25l{}0,1 [?12l[?25h[?25l{}09[?12l[?25h[?25l8[?12l[?25h[?25l7[?12l[?25h[?25l6[?12l[?25h[?25l5[?12l[?25h[?25l4[?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l1[?12l[?25h[?25l0[?12l[?25h[?25l499[?12l[?25h[?25l8,0-1[?12l[?25h[?25l7,1 [?12l[?25h[?25l6,0-1[?12l[?25h[?25l5,1 [?12l[?25h[?25l4[?12l[?25h[?25l3[?12l[?25h[?25l2,0-1[?12l[?25h[?25l1,1-8[?12l[?25h[?25l0[?12l[?25h[?25l89[?12l[?25h[?25l8[?12l[?25h[?25l7,1 [?12l[?25h[?25l6[?12l[?25h[?25l5[?12l[?25h[?25l4,1-8[?12l[?25h[?25l3,1 [?12l[?25h[?25l2,1-8[?12l[?25h[?25l1[?12l[?25h[?25l0,1 [?12l[?25h[?25l79[?12l[?25h[?25l8[?12l[?25h[?25l7,1-8[?12l[?25h[?25l6[?12l[?25h[?25l5[?12l[?25h[?25l4,1 [?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l1[?12l[?25h[?25l0[?12l[?25h[?25l// case 'v':469,199%[?12l[?25h[?25l break;468,1-899%[?12l[?25h[?25l continuous = 0;467,1-899%[?12l[?25h[?25l shortrun = 1;466,1-899%[?12l[?25h[?25l case 's':465,1-898%[?12l[?25h[?25l break;464,1-898%[?12l[?25h[?25l shortrun = 0;463,1-898%[?12l[?25h[?25l continuous = 1;462,1-898%[?12l[?25h[?25l case 'c':461,1-898%[?12l[?25h[?25l {460,1-897%[?12l[?25h[?25l switch (c)459,197%[?12l[?25h[?25l while ((c = getopt (argc, argv, "csi:n")) != -1)458,197%[?12l[?25h[?25l opterr = 0;457,197%[?12l[?25h[?25l /* don't want getopt to moan - I can do that just fine thanks! */456,197%[?12l[?25h[?25l455,0-196%[?12l[?25h[?25l verbose = 0;454,196%[?12l[?25h[?25l /* set defaults */453,196%[?12l[?25h[?25l452,0-196%[?12l[?25h[?25l char c;451,195%[?12l[?25h[?25l450,0-195%[?12l[?25h[?25lvoid processArgs (int argc, char **argv ) {449,195%[?12l[?25h[?25l */448,195%[?12l[?25h[?25l * Process the arguments.447,195%[?12l[?25h[?25l/*446,194%[?12l[?25h[?25l445,0-194%[?12l[?25h[?25l444,0-194%[?12l[?25h[?25l}443,194%[?12l[?25h[?25l writeReg(&nf2, SERIAL_TEST_CTRL_1_REG, 0);442,194%[?12l[?25h[?25l writeReg(&nf2, SERIAL_TEST_CTRL_0_REG, 0);441,193%[?12l[?25h[?25l writeReg(&nf2, SERIAL_TEST_CTRL_REG, 0);440,193%[?12l[?25h[?25l //writeReg(&nf2, SERIAL_TEST_CTRL_REG, SERIAL_TEST_GLBL_CTRL_NONSTOP);439,193%[?12l[?25h[?25l writeReg(&nf2, SERIAL_TEST_CTRL_REG, SERIAL_TEST_GLBL_CTRL_RESTART);438,193%[?12l[?25h[?25l437,0-192%[?12l[?25h[?25l writeReg(&nf2, DRAM_TEST_CTRL_REG, DRAM_TEST_CTRL_REPEAT);436,192%[?12l[?25h[?25l usleep(100000);435,192%[?12l[?25h[?25l writeReg(&nf2, DRAM_TEST_CTRL_REG, 0x0);434,192%[?12l[?25h[?25l writeReg(&nf2, DRAM_TEST_EN_REG, DRAM_TEST_ENABLE_ENABLE_MASK);433,192%[?12l[?25h[?25l SRAM_TEST_ENABLE_SRAM_EN_MASK);432,191%[?12l[?25h[?25l SRAM_TEST_ENABLE_TEST_EN_MASK |431,191%[?12l[?25h[?25l writeReg(&nf2, SRAM_TEST_EN_REG,430,191%[?12l[?25h[?25l429,0-191%[?12l[?25h[?25l writeReg(&nf2, SRAM_TEST_RAND_SEED_LO_REG, data2);428,191%[?12l[?25h[?25l writeReg(&nf2, SRAM_TEST_RAND_SEED_HI_REG, data1 & 0xf);427,190%[?12l[?25h[?25l data2 = lrand48();426,190%[?12l[?25h[?25l data1 = lrand48();425,190%[?12l[?25h[?25l // program h/w random test with a different test seed for each iteration424,190%[?12l[?25h[?25l423,0-189%[?12l[?25h[?25l move(10,0);422,189%[?12l[?25h[?25l unsigned int data1, data2;421,189%[?12l[?25h[?25l420,0-189%[?12l[?25h[?25l int i;419,189%[?12l[?25h[?25l unsigned int val;418,188%[?12l[?25h[?25lvoid reset_tests(void) {417,188%[?12l[?25h[?25l// Reset the status of all tests416,188%[?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l9[?12l[?25h[?25l20,0-1[?12l[?25h[?25l1,1 [?12l[?25h[?25l2[?12l[?25h[?25l3,0-1[?12l[?25h[?25l4,1 [?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l9,0-1[?12l[?25h[?25l30,1 [?12l[?25h[?25l1[?12l[?25h[?25l2[?12l[?25h[?25l3[?12l[?25h[?25l4[?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7,0-1[?12l[?25h[?25l8,1 [?12l[?25h[?25l9[?12l[?25h[?25l40[?12l[?25h[?25l1[?12l[?25h[?25l2[?12l[?25h[?25l{}3[?12l[?25h[?25l{}4,0-1[?12l[?25h[?25l5[?12l[?25h[?25l6,1 [?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l9[?12l[?25h[?25l50,0-1[?12l[?25h[?25l1,1 [?12l[?25h[?25l2,0-1[?12l[?25h[?25l3,1 [?12l[?25h[?25l4[?12l[?25h[?25l5,0-1[?12l[?25h[?25l6,1 [?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l  switch (c)459,188%[?12l[?25h[?25l  {460,1-888%[?12l[?25h[?25l  case 'c':461,1-889%[?12l[?25h[?25l  continuous = 1;462,1-889%[?12l[?25h[?25l  shortrun = 0;463,1-889%[?12l[?25h[?25l  break;464,1-889%[?12l[?25h[?25l  case 's':465,1-889%[?12l[?25h[?25l  shortrun = 1;466,1-890%[?12l[?25h[?25l  continuous = 0;467,1-890%[?12l[?25h[?25l  break;468,1-890%[?12l[?25h[?25l // case 'v':469,190%[?12l[?25h[?25l // verbose = 1;470,191%[?12l[?25h[?25l // break;471,191%[?12l[?25h[?25l // case 'l': /* log file */472,191%[?12l[?25h[?25l // log_file_name = optarg;473,191%[?12l[?25h[?25l // break;474,191%[?12l[?25h[?25l  case 'i': /* interface name */475,1-892%[?12l[?25h[?25l  nf2.device_name = optarg;476,1-892%[?12l[?25h[?25l  break;477,1-892%[?12l[?25h[?25l  case 'n': /* without SATA test */478,192%[?12l[?25h[?25l  no_sata_flg = 1;479,192%[?12l[?25h[?25l  break;480,193%[?12l[?25h[?25l  case '?':481,1-893%[?12l[?25h[?25l  if (isprint (optopt))482,1-893%[?12l[?25h[?25l  fprintf (stderr, "Unknown option `-%c'.\n", optopt);483,193%[?12l[?25h[?25l  else484,1-894%[?12l[?25h[?25l  fprintf (stderr,485,194%[?12l[?25h[?25l  "Unknown option character `\\x%x'.\n",486,194%[?12l[?25h[?25l  optopt);487,194%[?12l[?25h[?25l  default:488,1-894%[?12l[?25h[?25l  usage(argv[0]);489,1-895%[?12l[?25h[?25l  exit(1);490,1-895%[?12l[?25h[?25l  }491,1-895%[?12l[?25h[?25l 492,0-195%[?12l[?25h[?25l // if (verbose) {493,195%[?12l[?25h[?25l // printf ("logfile = %s. bin file = %s\n", log_file_name, bin_file_name);494,196%[?12l[?25h[?25l // }495,196%[?12l[?25h[?25l 496,0-196%[?12l[?25h[?25l }497,196%[?12l[?25h[?25l 498,0-197%[?12l[?25h[?25l /*499,197%[?12l[?25h[?25l  * Describe usage of this program.500,197%[?12l[?25h[?25l  */501,197%[?12l[?25h[?25l void usage (char *prog) {502,197%[?12l[?25h[?25l  printf("Usage: %s [filename.bin | filename.bit]\n", prog);503,198%[?12l[?25h[?25l  printf("\nOptions: -l (default is stdout).\n");504,198%[?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l1[?12l[?25h[?25l0[?12l[?25h[?25l499[?12l[?25h[?25l8,0-1[?12l[?25h[?25l7,1 [?12l[?25h[?25l6,0-1[?12l[?25h[?25l5,1 [?12l[?25h[?25l4[?12l[?25h[?25l3[?12l[?25h[?25l2,0-1[?12l[?25h[?25l1,1-8[?12l[?25h[?25l0[?12l[?25h[?25l89[?12l[?25h[?25l8[?12l[?25h[?25l7,1 [?12l[?25h[?25l6[?12l[?25h[?25l5[?12l[?25h[?25l4,1-8[?12l[?25h[?25l3,1 [?12l[?25h[?25l2,1-8[?12l[?25h[?25l1[?12l[?25h[?25l0,1 [?12l[?25h[?25l79[?12l[?25h[?25l8[?12l[?25h[?25l7,1-8[?12l[?25h[?25l6[?12l[?25h[?25l5[?12l[?25h[?25l4,1 [?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l1[?12l[?25h[?25l0[?12l[?25h[?25l69[?12l[?25h[?25l8,1-8[?12l[?25h[?25l7[?12l[?25h[?25l6[?12l[?25h[?25l5[?12l[?25h[?25l4[?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l case 'c':461,1-898%[?12l[?25h[?25l {460,1-897%[?12l[?25h[?25l switch (c)459,197%[?12l[?25h[?25l while ((c = getopt (argc, argv, "csi:n")) != -1)458,197%[?12l[?25h[?25l opterr = 0;457,197%[?12l[?25h[?25l /* don't want getopt to moan - I can do that just fine thanks! */456,197%[?12l[?25h[?25l455,0-196%[?12l[?25h[?25l verbose = 0;454,196%[?12l[?25h[?25l5,0-1[?12l[?25h[?25l6,1 [?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l9[?12l[?25h[?25l60,1-8[?12l[?25h[?25l1[?12l[?25h[?25l2[?12l[?25h[?25l3[?12l[?25h[?25l4[?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l9,1 [?12l[?25h[?25l70[?12l[?25h[?25l1[?12l[?25h[?25l2[?12l[?25h[?25l3[?12l[?25h[?25l4[?12l[?25h[?25l5,1-8[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8,1 [?12l[?25h[?25l9[?12l[?25h[?25l80[?12l[?25h[?25l1,1-8[?12l[?25h[?25l2[?12l[?25h[?25l3,1 [?12l[?25h[?25l4,1-8[?12l[?25h[?25l5,1 [?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8,1-8[?12l[?25h[?25l7,1 [?12l[?25h[?25l6[?12l[?25h[?25l5[?12l[?25h[?25l4,1-8[?12l[?25h[?25l3,1 [?12l[?25h[?25l2,1-8[?12l[?25h[?25l1[?12l[?25h[?25l0,1 [?12l[?25h[?25l79[?12l[?25h[?25l80[?12l[?25h[?25l1,1-8[?12l[?25h[?25l2[?12l[?25h[?25l3,1 [?12l[?25h[?25l4,1-8[?12l[?25h[?25l5,1 [?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8,1-8[?12l[?25h[?25l9[?12l[?25h[?25l90[?12l[?25h[?25l1[?12l[?25h[?25l2,0-1[?12l[?25h[?25l3,1 [?12l[?25h[?25l4[?12l[?25h[?25l5[?12l[?25h[?25l6,0-1[?12l[?25h[?25l }497,196%[?12l[?25h[?25l 498,0-197%[?12l[?25h[?25l /*499,197%[?12l[?25h[?25l  * Describe usage of this program.500,197%[?12l[?25h[?25l  */501,197%[?12l[?25h[?25l void usage (char *prog) {502,197%[?12l[?25h[?25l  printf("Usage: %s [filename.bin | filename.bit]\n", prog);503,198%[?12l[?25h[?25l  printf("\nOptions: -l (default is stdout).\n");504,198%[?12l[?25h[?25l  printf(" -i : interface name.\n");505,198%[?12l[?25h[?25l4[?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l1[?12l[?25h[?25l0[?12l[?25h[?25l499[?12l[?25h[?25l8,0-1[?12l[?25h[?25l7,1 [?12l[?25h[?25l6,0-1[?12l[?25h[?25l5,1 [?12l[?25h[?25l4[?12l[?25h[?25l3[?12l[?25h[?25l2,0-1[?12l[?25h[?25l1,1-8[?12l[?25h[?25l0[?12l[?25h[?25l89[?12l[?25h[?25l8[?12l[?25h[?25l7,1 [?12l[?25h[?25l6[?12l[?25h[?25l5[?12l[?25h[?25l4,1-8[?12l[?25h[?25l3,1 [?12l[?25h[?25l2,1-8[?12l[?25h[?25l1[?12l[?25h[?25l0,1 [?12l[?25h[?25l79[?12l[?25h[?25l8[?12l[?25h[?25l7,1-8[?12l[?25h[?25l6[?12l[?25h[?25l5[?12l[?25h[?25l4,1 [?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l1[?12l[?25h[?25l0[?12l[?25h[?25l69[?12l[?25h[?25l8,1-8[?12l[?25h[?25l7[?12l[?25h[?25l6[?12l[?25h[?25l5[?12l[?25h[?25l4[?12l[?25h[?25l3[?12l[?25h[?25l continuous = 1;462,1-898%[?12l[?25h[?25l case 'c':461,1-898%[?12l[?25h[?25l {460,1-897%[?12l[?25h[?25l switch (c)459,197%[?12l[?25h[?25l while ((c = getopt (argc, argv, "csi:n")) != -1)458,197%[?12l[?25h[?25l opterr = 0;457,197%[?12l[?25h[?25l /* don't want getopt to moan - I can do that just fine thanks! */456,197%[?12l[?25h[?25l455,0-196%[?12l[?25h[?25l verbose = 0;454,196%[?12l[?25h[?25l /* set defaults */453,196%[?12l[?25h[?25l452,0-196%[?12l[?25h[?25l char c;451,195%[?12l[?25h[?25l450,0-195%[?12l[?25h[?25lvoid processArgs (int argc, char **argv ) {449,195%[?12l[?25h[?25l */448,195%[?12l[?25h[?25l * Process the arguments.447,195%[?12l[?25h[?25l/*446,194%[?12l[?25h[?25l445,0-194%[?12l[?25h[?25l444,0-194%[?12l[?25h[?25l5[?12l[?25h[?25l6,1 [?12l[?25h[?25l7[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l9[?12l[?25h[?25l6[?12l[?25h[?25l/\search hit BOTTOM, continuing at TOPint verbose = 0; int continuous = 0; int shortrun = 1; int no_sata_flg = 0; FILE * log_file; WINDOW *w; /* Function declarations */ void mainContinuous(void); void mainOneShot(void); //void init_work(void); void reset_tests(void); //void show_stats (int loop_iter); //bool show_status_serial_test(void); //bool show_status_sram_test(void); //bool show_status_dram_test(void); //bool show_status_mii_test(void); //bool show_status_phy_test(void); //bool show_status_reg_test(void); //void sram_sw_test(SW_TEST_EFFORT_LEVEL ); void processArgs (int, char **); void usage (char*); void run_continuous(void); void reset_continuous(void); void stop_continuous(void); void sigint_handler(int signum); void reset_board(void); void title_bar(void); void clear_line(void); #define NUM_TESTS 8 /* Selftest module interface */ struct test_module modules[NUM_TESTS] = { { "Clock select", clkResetContinuous, clkShowStatusContinuous, clkStopContinuous, clkGetResult, }, { "Register interface",75,611% search hit BOTTOM, continuing at TOP75,611%[?12l[?25h[?25l/\ serialGetResult, }, { "DMA interface", dmaResetContinuous, dmaShowStatusContinuous, dmaStopContinuous, dmaGetResult, }, }; /* * Main function */ int main(int argc, char *argv[]) { // Set the default device nf2.device_name = DEFAULT_IFACE; // Process the command line arguments processArgs(argc, argv); // Check that the interface is valid and open it if possible if (check_iface(&nf2)) { exit(1); } if (openDescriptor(&nf2)) { exit(1); } // Verify that the correct device is downloaded if (!checkVirtexBitfile(&nf2, DEVICE_PROJ_DIR, DEVICE_MAJOR, DEVICE_MINOR, VERSION_ANY, DEVICE_MAJOR, DEVICE_MINOR, VERSION_ANY)) { fprintf(stderr, "%s\n", getVirtexBitfileErr()); exit(1); } else { printf(getDeviceInfoStr(&nf2)); }156,328%[?12l[?25h[?25l7,0-1[?12l[?25h[?25l8,3 [?12l[?25h[?25l9[?12l[?25h[?25l {  }60[?12l[?25h[?25l{ }1[?12l[?25h[?25l{  }2[?12l[?25h[?25l{ }3[?12l[?25h[?25l {  }4[?12l[?25h[?25l{ }5[?12l[?25h[?25l{  }6[?12l[?25h[?25l{ }7,0-1[?12l[?25h[?25l8,3 [?12l[?25h[?25l9[?12l[?25h[?25l70,1-8[?12l[?25h[?25l1[?12l[?25h[?25l2,3 [?12l[?25h[?25l3[?12l[?25h[?25l{}4[?12l[?25h[?25l{}5[?12l[?25h[?25l6[?12l[?25h[?25l{  }7[?12l[?25h[?25l { }178,0-128%[?12l[?25h[?25l  // Add a signal handler179,328%[?12l[?25h[?25l  signal(SIGINT, sigint_handler);180,329%[?12l[?25h[?25l 181,0-129%[?12l[?25h[?25l  // Measure the clock rates182,329%[?12l[?25h[?25l  measureClocks();183,329%[?12l[?25h[?25l 184,0-130%[?12l[?25h[?25l  // Run the appropriate test185,330%[?12l[?25h[?25l  if (continuous) {186,330%[?12l[?25h[?25l  mainContinuous();187,330%[?12l[?25h[?25l { }188,330%[?12l[?25h[?25l { } else if (shortrun) {189,331%[?12l[?25h[?25l  mainOneShot();190,331%[?12l[?25h[?25l { }191,331%[?12l[?25h[?25l { }192,0-131%[?12l[?25h[?25l  // Close the network descriptor193,331%[?12l[?25h[?25l  closeDescriptor(&nf2);194,332%[?12l[?25h[?25l 195,0-132%[?12l[?25h[?25l  return 0;196,332%[?12l[?25h[?25l }197,132%[?12l[?25h[?25l 198,0-133%[?12l[?25h[?25l /*199,233%[?12l[?25h[?25l8,0-1[?12l[?25h[?25l7,1 [?12l[?25h[?25l6,3[?12l[?25h[?25l5,0-1[?12l[?25h[?25l4,3 [?12l[?25h[?25l3[?12l[?25h[?25l2,0-1[?12l[?25h[?25l{  }1,3 [?12l[?25h[?25l{ }0[?12l[?25h[?25l89[?12l[?25h[?25l{  }8[?12l[?25h[?25l{ }7[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l{  }8[?12l[?25h[?25l{ }9[?12l[?25h[?25l90[?12l[?25h[?25l{  }1[?12l[?25h[?25l{ }0[?12l[?25h[?25l4[?12l[?25h[?25l5[?12l[?25h[?25l89[?12l[?25h[?25l8[?12l[?25h[?25l()11[?12l[?25h[?25l()2[?12l[?25h[?25l/\ writeReg(&nf2, SERIAL_TEST_CTRL_1_REG, 0); } /* * Process the arguments. */ void processArgs (int argc, char **argv ) { char c; /* set defaults */ verbose = 0; /* don't want getopt to moan - I can do that just fine thanks! */ opterr = 0; while ((c = getopt (argc, argv, "csi:n")) != -1) switch (c) { case 'c': continuous = 1; shortrun = 0; break; case 's': shortrun = 1; continuous = 0; break; // case 'v': // verbose = 1; // break; // case 'l': /* log file */ // log_file_name = optarg; // break; case 'i': /* interface name */ nf2.device_name = optarg; break; case 'n': /* without SATA test */ no_sata_flg = 1; break; case '?': if (isprint (optopt)) fprintf (stderr, "Unknown option `-%c'.\n", optopt); else463,6-13 94%[?12l[?25h[?25l4[?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8[?12l[?25h[?25l9,8[?12l[?25h[?25l70[?12l[?25h[?25l1[?12l[?25h[?25l2[?12l[?25h[?25l3[?12l[?25h[?25l4[?12l[?25h[?25l5,6[?12l[?25h[?25l6[?12l[?25h[?25l7[?12l[?25h[?25l8,13 [?12l[?25h[?25l9[?12l[?25h[?25l80,12[?12l[?25h[?25l1,6-13[?12l[?25h[?25l2[?12l[?25h[?25l1[?12l[?25h[?25l0,12 [?12l[?25h[?25l79,13[?12l[?25h[?25l8[?12l[?25h[?25l7,6-13[?12l[?25h[?25l6[?12l[?25h[?25l5[?12l[?25h[?25l4,8[?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l1[?12l[?25h[?25l0[?12l[?25h[?25l69[?12l[?25h[?25l8,6[?12l[?25h[?25l7[?12l[?25h[?25l6[?12l[?25h[?25l5[?12l[?25h[?25l4[?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l/\463,6-13 94%[?12l[?25h[?25l466,6-13 94%[?12l[?25h[?25lsearch hit BOTTOM, continuing at TOP#include "selftest_sram.h" #include "selftest_serial.h" #include "selftest_phy.h" #include "selftest_mdio.h" #include "selftest_reg.h" #include "selftest_clk.h" #include "selftest_dma.h" #define PATHLEN 80 #define DEFAULT_IFACE "nf2c0" #define SELFTEST_VERSION "1.00 alpha" #define ONE_SHOT_ITER 5 typedef enum {LOW = 0, HIGH = 1} SW_TEST_EFFORT_LEVEL; /* Global vars */ struct nf2device nf2; int verbose = 0; int continuous = 0; int shortrun = 1; int no_sata_flg = 0; FILE * log_file; WINDOW *w; /* Function declarations */ void mainContinuous(void); void mainOneShot(void); //void init_work(void); void reset_tests(void); //void show_stats (int loop_iter); //bool show_status_serial_test(void); //bool show_status_sram_test(void); //bool show_status_dram_test(void); //bool show_status_mii_test(void); //bool show_status_phy_test(void); //bool show_status_reg_test(void); //void sram_sw_test(SW_TEST_EFFORT_LEVEL ); void processArgs (int, char **); void usage (char*); void run_continuous(void);56,57% search hit BOTTOM, continuing at TOP56,57%[?12l[?25h[?25l/\ // Verify that the correct device is downloaded if (!checkVirtexBitfile(&nf2, DEVICE_PROJ_DIR, DEVICE_MAJOR, DEVICE_MINOR, VERSION_ANY, DEVICE_MAJOR, DEVICE_MINOR, VERSION_ANY)) { fprintf(stderr, "%s\n", getVirtexBitfileErr()); exit(1); } else { printf(getDeviceInfoStr(&nf2)); } // Add a signal handler signal(SIGINT, sigint_handler); // Measure the clock rates measureClocks(); // Run the appropriate test if (continuous) { mainContinuous(); } else if (shortrun) { mainOneShot(); } // Close the network descriptor closeDescriptor(&nf2); return 0; } /* * "Main" function for continuous mode */ void mainContinuous(void) { // Set up curses w = initscr(); cbreak(); halfdelay(1); noecho(); //init_work(); //initialization. one time effort189,1235%[?12l[?25h[?25l90[?12l[?25h[?25l5 [?12l[?25h[?25l/\ // Run the test in continuous mode run_continuous(); stop_continuous(); // End the curses endwin(); } /* * "Main" function for one-shot mode */ void mainOneShot(void)223,638%[?12l[?25h[?25l {224,138%[?12l[?25h[?25l  int i;225,638%[?12l[?25h[?25l  int failed = 0;226,639%[?12l[?25h[?25l 227,0-139%[?12l[?25h[?25l  // Reset the board and initialize the tests228,639%[?12l[?25h[?25l  reset_board();229,639%[?12l[?25h[?25l  reset_continuous();230,639%[?12l[?25h[?25l 231,0-140%[?12l[?25h[?25l  // Run the test in one-shot mode mode232,640%[?12l[?25h[?25l  printf("NetFPGA selftest %s\n", SELFTEST_VERSION);233,640%[?12l[?25h[?25l  printf("Running");234,640%[?12l[?25h[?25l  fflush(stdout);235,640%[?12l[?25h[?25l  for (i = 0; i < ONE_SHOT_ITER; i++) {236,641%[?12l[?25h[?25l  sleep(1);237,641%[?12l[?25h[?25l  printf(".");238,641%[?12l[?25h[?25l  fflush(stdout);239,641%[?12l[?25h[?25l { }240,342%[?12l[?25h[?25l {} printf(" ");241,642%[?12l[?25h[?25l 242,0-142%[?12l[?25h[?25l  // Verify the results243,642%[?12l[?25h[?25l  for (i = 0; i < NUM_TESTS; i++) {244,642%[?12l[?25h[?25l  if (!modules[i].get_result()) {245,643%[?12l[?25h[?25l  if (!failed)246,643%[?12l[?25h[?25l  printf("FAILED. Failing tests: ");247,643%[?12l[?25h[?25l  else248,643%[?12l[?25h[?25l  printf(", ");249,643%[?12l[?25h[?25l  printf(modules[i].name);250,644%[?12l[?25h[?25l 251,0-144%[?12l[?25h[?25l  // Record that the tests have failed252,644%[?12l[?25h[?25l  failed = 1;253,644%[?12l[?25h[?25l2[?12l[?25h[?25l1,0-1[?12l[?25h[?25l0,6 [?12l[?25h[?25l49[?12l[?25h[?25l8[?12l[?25h[?25l7[?12l[?25h[?25l6[?12l[?25h[?25l5[?12l[?25h[?25l4[?12l[?25h[?25l3[?12l[?25h[?25l2,0-1[?12l[?25h[?25l1,6 [?12l[?25h[?25l{}0,3[?12l[?25h[?25l{}39,6[?12l[?25h[?25l8[?12l[?25h[?25l7[?12l[?25h[?25l6[?12l[?25h[?25l5[?12l[?25h[?25l4[?12l[?25h[?25l3[?12l[?25h[?25l2[?12l[?25h[?25l1,0-1[?12l[?25h[?25l0,6 [?12l[?25h[?25l29[?12l[?25h[?25l3[?12l[?25h[?25l/\ * Clear a line */ void clear_line(void) { int n; n = COLS; for (; n > 0; n--) addch(' '); } /* * Run the program in continuous mode */ void run_continuous(void) { int ch = ERR; int count; int prev_lines; int prev_cols; int i; // Reset the board and initialize the tests reset_board(); reset_continuous(); // Run the tests continuously and wait while (1) { // Remember the screen dimensions prev_lines = LINES; prev_cols = COLS; // Clear the screen and move to the top corner erase(); move(0,0); // Display a title bar title_bar(); // Display the output of the tests move(2,0); for (i = 0; i < NUM_TESTS; i++) { modules[i].show_status_continuous();301,359%[?12l[?25h[?25l/\ move(LINES - 2,0); // Draw the screen refresh(); // Sleep for a while, looking for key presses count = 0; ch = ERR; while (count < 10 && ch != 'q' && ch != 'Q' && prev_lines == LINES && prev_cols == COLS) { ch = getch(); count++; } if (ch == 'q' || ch == 'Q') { return; } } } /* * Reset the board */ void reset_board(void) { u_int val; /* Read the current value of the control register so that we can modify * it to do a reset */ readReg(&nf2, CPCI_CTRL_REG, &val); /* Write to the control register to reset it */ writeReg(&nf2, CPCI_CTRL_REG, val | CPCI_CTRL_CNET_RESET); } /* * Handle SIGINT gracefully */ void sigint_handler(int signum) { if (signum == SIGINT) { endwin(); if (continuous) stop_continuous(); printf("Caught SIGINT. Exiting...\n");354,670%[?12l[?25h[?25l5[?12l[?25h[?25l/\search hit BOTTOM, continuing at TOPWINDOW *w; /* Function declarations */ void mainContinuous(void); void mainOneShot(void); //void init_work(void); void reset_tests(void); //void show_stats (int loop_iter); //bool show_status_serial_test(void); //bool show_status_sram_test(void); //bool show_status_dram_test(void); //bool show_status_mii_test(void); //bool show_status_phy_test(void); //bool show_status_reg_test(void); //void sram_sw_test(SW_TEST_EFFORT_LEVEL ); void processArgs (int, char **); void usage (char*); void run_continuous(void); void reset_continuous(void); void stop_continuous(void); void sigint_handler(int signum); void reset_board(void); void title_bar(void); void clear_line(void); #define NUM_TESTS 8 /* Selftest module interface */ struct test_module modules[NUM_TESTS] = { { "Clock select", clkResetContinuous, clkShowStatusContinuous, clkStopContinuous, clkGetResult, }, { "Register interface", regResetContinuous, regShowStatusContinuous, regStopContinuous, regGetResult, }, {81,612% search hit BOTTOM, continuing at TOP81,612%[?12l[?25h[?25l/\ noecho(); //init_work(); //initialization. one time effort // Run the test in continuous mode run_continuous(); stop_continuous(); // End the curses endwin(); } /* * "Main" function for one-shot mode */ void mainOneShot(void) { int i; int failed = 0; // Reset the board and initialize the tests reset_board(); reset_continuous(); // Run the test in one-shot mode mode printf("NetFPGA selftest %s\n", SELFTEST_VERSION); printf("Running"); fflush(stdout); for (i = 0; i < ONE_SHOT_ITER; i++) { sleep(1); printf("."); fflush(stdout); } printf(" "); // Verify the results for (i = 0; i < NUM_TESTS; i++) { if (!modules[i].get_result()) { if (!failed) printf("FAILED. Failing tests: "); else printf(", "); printf(modules[i].name);229,344%[?12l[?25h[?25l30[?12l[?25h[?25l/\ */ void clear_line(void) { int n; n = COLS; for (; n > 0; n--) addch(' '); } /* * Run the program in continuous mode */ void run_continuous(void) { int ch = ERR; int count; int prev_lines; int prev_cols; int i; // Reset the board and initialize the tests reset_board(); reset_continuous(); // Run the tests continuously and wait while (1) { // Remember the screen dimensions prev_lines = LINES; prev_cols = COLS; // Clear the screen and move to the top corner erase(); move(0,0); // Display a title bar title_bar(); // Display the output of the tests move(2,0); for (i = 0; i < NUM_TESTS; i++) { modules[i].show_status_continuous(); }302,359%[?12l[?25h[?25l/\ writeReg(&nf2, CPCI_CTRL_REG, val | CPCI_CTRL_CNET_RESET); } /* * Handle SIGINT gracefully */ void sigint_handler(int signum) { if (signum == SIGINT) { endwin(); if (continuous) stop_continuous(); printf("Caught SIGINT. Exiting...\n"); exit(0); } } /* * Invoke the reset functions for continuous mode */ void reset_continuous(void) { int i; for (i = 0; i < NUM_TESTS; i++) { modules[i].reset_continuous(); } } /* * Invoke the stop functions for continuous mode */ void stop_continuous(void) { int i; for (i = 0; i < NUM_TESTS; i++) { modules[i].stop_continuous(); } } //initialize. this is one time effort /*void init_work() { struct timeval tv;383,676%[?12l[?25h[?25l4[?12l[?25h[?25l5,0-1[?12l[?25h[?25l6,6 [?12l[?25h[?25l7[?12l[?25h[?25l/\387,1676%[?12l[?25h[?25lsearch hit BOTTOM, continuing at TOPint no_sata_flg = 0; FILE * log_file; WINDOW *w; /* Function declarations */ void mainContinuous(void); void mainOneShot(void); //void init_work(void); void reset_tests(void); //void show_stats (int loop_iter); //bool show_status_serial_test(void); //bool show_status_sram_test(void); //bool show_status_dram_test(void); //bool show_status_mii_test(void); //bool show_status_phy_test(void); //bool show_status_reg_test(void); //void sram_sw_test(SW_TEST_EFFORT_LEVEL ); void processArgs (int, char **); void usage (char*); void run_continuous(void); void reset_continuous(void); void stop_continuous(void); void sigint_handler(int signum); void reset_board(void); void title_bar(void); void clear_line(void); #define NUM_TESTS 8 /* Selftest module interface */ struct test_module modules[NUM_TESTS] = { { "Clock select", clkResetContinuous, clkShowStatusContinuous, clkStopContinuous, clkGetResult, }, { "Register interface", regResetContinuous, regShowStatusContinuous, regStopContinuous,78,611% search hit BOTTOM, continuing at TOP78,611%[?12l[?25h[?25l/\ //init_work(); //initialization. one time effort // Run the test in continuous mode run_continuous(); stop_continuous(); // End the curses endwin(); } /* * "Main" function for one-shot mode */ void mainOneShot(void) { int i; int failed = 0; // Reset the board and initialize the tests reset_board(); reset_continuous(); // Run the test in one-shot mode mode printf("NetFPGA selftest %s\n", SELFTEST_VERSION); printf("Running"); fflush(stdout); for (i = 0; i < ONE_SHOT_ITER; i++) { sleep(1); printf("."); fflush(stdout); } printf(" "); // Verify the results for (i = 0; i < NUM_TESTS; i++) { if (!modules[i].get_result()) { if (!failed) printf("FAILED. Failing tests: "); else printf(", "); printf(modules[i].name);230,344%[?12l[?25h[?25l:[?12l[?25hq[?25l[?12l[?25h [?25l[?1l>[?12l[?25h[?1049l]0;netfpga@node1-1: ~/netfpga/projects/selftest/swnetfpga@node1-1:~/netfpga/projects/selftest/sw$ pwd /home/netfpga/netfpga/projects/selftest/sw ]0;netfpga@node1-1: ~/netfpga/projects/selftest/swnetfpga@node1-1:~/netfpga/projects/selftest/sw$ pwdvi selftest.c sudo su - ]0;root@node1-1.sb9.orbit-lab.org: ~root@node1-1:~# exitls -al~netfpga/netfpga/projects/selftest/sw/selftest -ncn Found net device: nf2c0 CPCI Information ---------------- Version: 4 (rev 1) Device (Virtex) Information --------------------------- Project directory: selftest Project name: Selftest Project description: NetFPGA selftest -- exercises all major subsystems of the board Device ID: 5 Version: 1.1.0 Built against CPCI version: 4 (rev 1) [?1049h(B[?7h(B NetFPGA selftest v1.00 alpha (BClock test: pass Reg test: pass MDIO test: pass Phy 1: rev 1 up, 1000Base-TX full Phy 2: rev 1 up, 1000Base-TX full Phy 3: rev 1 up, 1000Base-TX full Phy 4: rev 1 up, 1000Base-TX full PHY test: fail Port 1: link w/ 4 Good: 10187 Bad: 7129 Port 2: link w/ 4 Good: 10050 Bad: 7268 Port 3: no link Good: 10110 Bad: 7209 Port 4: link w/ 3 Good: 10136 Bad: 7185 DRAM test: Iteration: 1 Good: 0 Bad: 0 B/W: nan Gbps SRAM test: Iteration: 1 Good: 0 Bad: 0 B/W: nan Gbps SATA Test Disabled DMA test: Iteration(one pkt write, read, compare): 40 Good: 40 Bad: 0 (BQ(B Quit no link Good: 30354 Bad: 77576no link Good: 28729 Bad: 79203293458589no link Good: 29590 Bad: 783453210.74 Gbps34 Good: 33 Bad: 0 B/W: 4.43 Gbps88 554571428455246314584053620144684link w/ 2 Good: 54014 Bad: 144291653.426766120 Good: 120 Bad: 0 link w/ 3 Good: 108530 Bad: 180155104779 Bad: 183907106286 Bad: 182401106771 Bad: 181917872.53100 Good: 99 Bad: 0 B/W: 4.43 Gbps66 253341225742485622305225048722859835122722785910 Good: 9 Bad: 0 B/W: 9.6634133 Bad: 0 B/W: 3.57 Gbps2020 47249796979660930338568839300639no link Good: 169723 Bad: 299757312 Bad: 0 B/W: 10.74 Gbps67667144 no link Good: 211272 Bad: 348601link w/ 4 Good: 203832 Bad: 35604220700052876link w/ 1 Good: 208196 Bad: 35168154200998288 link w/ 2 Good: 264351 Bad: 385917no link Good: 256176 Bad: 394093596699060126099289280763323293232 no link Good: 291105 Bad: 4495618146445920485535455134no link Good: 286984 Bad: 4536862091.3366659566 31030452075899072531991link w/ 1 Good: 303814 Bad: 5272503055035255632212799984.004040 626758784link w/ 3 Good: 350792 Bad: 5706674558776558357678637845471332331444 409550602296no link Good: 396727 Bad: 61512040227860957140414960770176636665888 28639736114143648788712033381919link w/ 3 Good: 422673 Bad: 67958098569998115252 5646873617740915751731no link Good: 447453 Bad: 745194no link Good: 450012 Bad: 7426363231104324313.8666 5094773558link w/ 1 Good: 493300 Bad: 789738link w/ 1 Good: 500140 Bad: 782899link w/ 2 Good: 502784 Bad: 7802564307656496060 link w/ 3 Good: 542714 Bad: 8307233525238848200no link Good: 532562 Bad: 840877no link Good: 535390 Bad: 83805065598979244 263607900226no link Good: 544878 Bad: 918956link w/ 1 Good: 552821 Bad: 911015559449078939833531530588 no link Good: 589948 Bad: 964283link w/ 3 Good: 569839 Bad: 984394no link Good: 578276 Bad: 975958815897264641400646387272 6090411035587no link Good: 587472 Bad: 1057158965481048083link w/ 3 Good: 600052 Bad: 1044580435498974.0166 link w/ 3 Good: 661762 Bad: 10732616395379548764889086135252578245565063163038080 no link Good: 708300 Bad: 111712085329140092link w/ 1 Good: 694944 Bad: 1130478no link Good: 698679 Bad: 112674487476463444 link w/ 3 Good: 727362 Bad: 1188455702901212917271312320269671722398598515069796688 45457251639link w/ 4 Good: 728623 Bad: 127758913930966904437892624253217307293.919292 no link Good: 807609 Bad: 1288999no link Good: 780960 Bad: 131564949197304632965863000265456362366 4044134656381257574430no link Good: 824013 Bad: 1362993828890581178733969551000 Good: 1000 Bad: 0 5954541785530203447198link w/ 4 Good: 842184 Bad: 1435219link w/ 3 Good: 847378 Bad: 143002660918308297 44 9057706202675530922672877958000393257745433624863629 88 5895899233927868530325no link Good: 940506 Bad: 1517688no link Good: 946070 Bad: 151212654596954.001212 link w/ 3 Good: 978182 Bad: 15704014540760317758698988964582840047639299282 66 21004029 Bad: 1634957699506903link w/ 4 Good: 983814 Bad: 1655174link w/ 3 Good: 990054 Bad: 164893570958626132020 5712072262link w/ 4 Good: 1022328 Bad: 170705511036480 Bad: 1692904no link Good: 1042795 Bad: 1686590271595944 44 310107718708no link Good: 1065288 Bad: 1754491no link Good: 1079883 Bad: 17398978630773347443201028 Good: 1027 Bad: 0 B/W: 3.94 Gbps88 no link Good: 1120144 Bad: 1790030link w/ 3 Good: 1082899 Bad: 1827276981358120421048308053487633626163232 59809840758112149179077link w/ 1 Good: 1137227 Bad: 1863342link w/ 2 Good: 1144086 Bad: 18564849829594766 link w/ 4 Good: 1212857 Bad: 1878109373864917103no link Good: 1189954 Bad: 19010143968479412282814412812784040 no link Good: 1238565 Bad: 1942792no link Good: 1198336 Bad: 1983022link w/ 1 Good: 1214971 Bad: 1966388no link Good: 1221913 Bad: 19594474336160944 578920138632162392055520no link Good: 1233431 Bad: 2038329link w/ 3 Good: 1240775 Bad: 203098665194934.0088 link w/ 3 Good: 1310997 Bad: 2051156link w/ 3 Good: 1268563 Bad: 2093591link w/ 2 Good: 1286136 Bad: 20760199356868588985222722615252 no link Good: 1356935 Bad: 2095614no link Good: 1313594 Bad: 2138956331667120885339157113396919006059266 7607916686731156211791no link Good: 1349858 Bad: 2193090no link Good: 1357662 Bad: 21852873249949346060 404857228485585597478477910255434link w/ 1 Good: 1385938 Bad: 224740765333273263.9544 579965741link w/ 3 Good: 1410843 Bad: 2312896link w/ 1 Good: 1430618 Bad: 2293122438804849388726059788 90275323857no link Good: 1441869 Bad: 237226462160351975no link Good: 1470538 Bad: 2343598101 Good: 100 Bad: 0 B/W: 11.42 Gbps939287272 link w/ 2 Good: 1512054 Bad: 23924776245144208183253421280919141261632142642566 no link Good: 1537494 Bad: 245743486368508562no link Good: 1507865 Bad: 248706651676678165439595898080 link w/ 3 Good: 1557093 Bad: 25282305046158070926726558600358715494587492914.0044 no link Good: 1610223 Bad: 2565495569436187767941496307link w/ 3 Good: 1588619 Bad: 25871031097526525188 link w/ 3 Good: 1655936 Bad: 261018060163864479624559641560no link Good: 1633881 Bad: 26322392116595829292 no link Good: 1675022 Bad: 268149019302737212link w/ 1 Good: 1642866 Bad: 27136495235470416254559291366 link w/ 3 Good: 1703966 Bad: 2742942link w/ 3 Good: 1646949 Bad: 27999612709897592280860660576326256243.96200200 no link Good: 1757036 Bad: 2780267no link Good: 1699281 Bad: 28380231723682813624733626803681209415857744 8899483870673008097622no link Good: 1754937 Bad: 2872765649906271422109190888 8080229100714771970384link w/ 4 Good: 1773088 Bad: 294500783475934622433972472391212 551553340link w/ 4 Good: 1793936 Bad: 30145588196738882283023678260764758574.0066 link w/ 3 Good: 1907383 Bad: 2991498no link Good: 1845379 Bad: 3053503no link Good: 1871499 Bad: 302738482133301675198591902020 no link Good: 1926459 Bad: 306282463015126269898269945990057988708323153824823144 link w/ 2 Good: 1953250 Bad: 3126433link w/ 1 Good: 1888537 Bad: 3191148link w/ 4 Good: 1915956 Bad: 3163730268701528174325756288 2006276637999408882291896856820151link w/ 3 Good: 1979641 Bad: 319043865090893232 no link Good: 2049328 Bad: 32111424829527751no link Good: 2011090 Bad: 3249382no link Good: 2022275 Bad: 32381999849239223.9766 link w/ 2 Good: 2068489 Bad: 3282379no link Good: 2000556 Bad: 335031429311321560link w/ 2 Good: 2040799 Bad: 3310073414039575684040 109072332194link w/ 3 Good: 2040096 Bad: 3401171link w/ 4 Good: 2069220 Bad: 33720488098460285328908944 no link Good: 2162202 Bad: 336945849242839234no link Good: 2121894 Bad: 340976911337399792654520232022988 link w/ 2 Good: 2187025 Bad: 3435032no link Good: 2115876 Bad: 350618245931761285792146414087456554.005252 207317505131346987775165396547054377619534832515050898866 46039842448link w/ 1 Good: 2187080 Bad: 3615768link w/ 2 Good: 2218032 Bad: 3584817no link Good: 2230404 Bad: 3572446324912212116060 230547087775no link Good: 2231180 Bad: 3662066no link Good: 2262554 Bad: 3630694750476182025485554244 no link Good: 2324533 Bad: 3659103488137348258087170276893481901598755898888 link w/ 2 Good: 2352968 Bad: 3721067link w/ 1 Good: 2275990 Bad: 379804630848865549link w/ 2 Good: 2321491 Bad: 3752547609382222213.977272 340609158343no link Good: 2328296 Bad: 3836139link w/ 4 Good: 2361162 Bad: 38032741742849015326175554866 no link Good: 2437465 Bad: 38173675836996464no link Good: 2391841 Bad: 3862993no link Good: 2405143 Bad: 38496925443888798080 link w/ 2 Good: 2460251 Bad: 38849747979296543link w/ 2 Good: 2413780 Bad: 3931448273719178587632132044 no link Good: 2484747 Bad: 39508754028374032786no link Good: 2437436 Bad: 3998188link w/ 3 Good: 2451363 Bad: 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360751329849489292 no link Good: 22768241 Bad: 35834408202773274918no link Good: 22345472 Bad: 36257179no link Good: 22466169 Bad: 361364844241828166 8725905792no link Good: 22045290 Bad: 3664775463711329334846522083943515514600600 836638468049383289611link w/ 2 Good: 22412705 Bad: 36370739link w/ 3 Good: 22533762 Bad: 3624968465484744 link w/ 4 Good: 22889700 Bad: 35984136146187276561653614084788663887202988818088 91097160532626583098404no link Good: 22485692 Bad: 36478543no link Good: 22607085 Bad: 3635715151506156141212 no link Good: 22940193 Bad: 36114437link w/ 4 Good: 22193796 Bad: 36860836514218540415link w/ 1 Good: 22635698 Bad: 3641893643484766 9327551750124613998887link w/ 1 Good: 22566891 Bad: 36578136388564564656581802020 3029449205973no link Good: 22281260 Bad: 36954163no link Good: 22602444 Bad: 36632981no link Good: 22724317 Bad: 3651110987771471344 link w/ 3 Good: 23048621 Bad: 36277198987857027035206107052142811830116160474688 no link Good: 23091512 Bad: 36324700link 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link Good: 23722929 Bad: 381339847675744040 29443252873no link Good: 23312763 Bad: 38634543no link Good: 23648541 Bad: 382987667569871610309870870744 no link Good: 24116102 Bad: 37921601329157047896933636836996635241071231424188 link w/ 3 Good: 24135261 Bad: 37992836link w/ 4 Good: 23350653 Bad: 38777446877104403908151773129254375745252 no link Good: 24188276 Bad: 380302163403025815468link w/ 2 Good: 23740395 Bad: 3847809967959505367680880766 link w/ 2 Good: 24230261 Bad: 38078627no link Good: 23443865 Bad: 38865024no link Good: 23781770 Bad: 38527120link w/ 2 Good: 23909305 Bad: 383995869841406060 no link Good: 24249367 Bad: 381499176150493778180007399213no link Good: 23927784 Bad: 3847150342419747344 77599212082884709001213274806622045541853426743790790688 966478343050618573894572734359740676060136540397272 link w/ 2 Good: 24340693 Bad: 38329782link w/ 1 Good: 23549323 Bad: 39121153link w/ 2 Good: 23889232 Bad: 38781246401779852681988747366 no link Good: 24393753 Bad: 38367118no link Good: 23601702 Bad: 39159170no link Good: 23941920 Bad: 38818953link w/ 2 Good: 24070565 Bad: 3869030951507300730068080 415120436142215612297026243588829no link Good: 24091250 Bad: 3876001532403944 34486507176link w/ 3 Good: 23639272 Bad: 3930239280939960726link w/ 3 Good: 24109992 Bad: 38831674658737288 link w/ 4 Good: 24487582 Bad: 3854447619158140479link w/ 1 Good: 24033606 Bad: 389984556280669256871061059292 no link Good: 24529216 Bad: 38593240no link Good: 23732159 Bad: 39390298no link Good: 24074583 Bad: 39047875no link Good: 24203979 Bad: 389184806160393866 4819766465449766463086link w/ 2 Good: 24092905 Bad: 39119949link w/ 1 Good: 24222540 Bad: 38990315327271800800 85695717543link w/ 3 Good: 23786180 Bad: 395170591298273415259642904360054720620544 638784548591838545550948255821108813124208122787393888 66772817270no link Good: 23865043 Bad: 39619001no link Good: 24209700 Bad: 39274345no link Good: 24339798 Bad: 3914424870972711212 85921885138268191754link w/ 2 Good: 24227959 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3980722671264475354386036025252 no link Good: 25064762 Bad: 39413636no link Good: 24250708 Bad: 40227691600737776643277074563265363566 link w/ 2 Good: 25084753 Bad: 39484042691459965link w/ 1 Good: 24619901 Bad: 39948896link w/ 2 Good: 24752194 Bad: 398166049870696060 137880521309link w/ 1 Good: 24321478 Bad: 40337712no link Good: 24672519 Bad: 3998667238049875420670170070370244 no link Good: 25178880 Bad: 39570704no link Good: 24361492 Bad: 40388094link w/ 2 Good: 24712921 Bad: 400366664545390413532363588 9793564204779004460979no link Good: 24731242 Bad: 40108742no link Good: 24863909 Bad: 3997607665769687272 226277704100405887524491link w/ 1 Good: 24758757 Bad: 4017162291618400387628780280166 454137536223528972482770092437689100801106991110835348080 link w/ 3 Good: 25290312 Bad: 3982085967532643640821338898365469556480327686744 no link Good: 25343368 Bad: 39858191link w/ 1 Good: 24519813 Bad: 40681748174004327558link w/ 1 Good: 25007518 Bad: 401940455490290188 63790928173no link Good: 24538783 Bad: 40753181no link Good: 24893605 Bad: 40398360no link Good: 25027388 Bad: 4026457887835349292 link w/ 3 Good: 25383006 Bad: 399993485659982575691188247047546033336325209686766 no link Good: 25436103 Bad: 40036650link w/ 3 Good: 24608917 Bad: 408638376460508154987777398022140014000900900 link w/ 4 Good: 25476841 Bad: 4008631044853391461950048355831813899142416354343344 no link Good: 25496056 Bad: 40157491no link Good: 24666271 Bad: 4098727723146630403link w/ 2 Good: 25157505 Bad: 40496046767676688 link w/ 2 Good: 25534452 Bad: 402094897035391040403609083037no link Good: 25195471 Bad: 40548474309100991212 no link Good: 25587574 Bad: 40246762link w/ 1 Good: 24755887 Bad: 4107845111353720803link w/ 3 Good: 25248311 Bad: 405860292313413366 614622310114no link Good: 24781558 Bad: 41143179link w/ 2 Good: 25139788 Bad: 40784950no link Good: 25274721 Bad: 406500184367662020 336948143599160215971no link Good: 25157914 Bad: 40857218932287219057682009944 link w/ 4 Good: 25685727 Bad: 404198018505454989link w/ 2 Good: 25209536 Bad: 408959943450760453983323288 373753258393link w/ 4 Good: 24901587 Bad: 41294339no link Good: 25260946 Bad: 409349819660799322414066653232 no link Good: 25756560 Bad: 40529761no link Good: 24919264 Bad: 41367058link w/ 2 Good: 25279221 Bad: 4100710241511587120943999866 link w/ 4 Good: 25788372 Bad: 4058834249898426817no link Good: 25310312 Bad: 41066405link w/ 3 Good: 25446472 Bad: 40930246653323314040 841425625687link w/ 4 Good: 25002275 Bad: 41464838link w/ 1 Good: 25362946 Bad: 4110416929927867838987666544 750998240no link Good: 25034616 Bad: 41522891no link Good: 25395852 Bad: 41161657no link Good: 25532280 Bad: 410252305150999888 no link Good: 25894223 Bad: 4075368152232956744141572337505082597083324324315252 link w/ 2 Good: 25939655 Bad: 40798646link w/ 4 Good: 25096879 Bad: 416414245911579189link w/ 1 Good: 25596129 Bad: 41142176658656466 9279483590214920779490link w/ 1 Good: 25511788 Bad: 413169103648881798198798976060 no link Good: 26012655 Bad: 40906436no link Good: 25167452 Bad: 417516413073188363no link Good: 25667905 Bad: 41251190609753153044 336037588link w/ 1 Good: 25186921 Bad: 41822569250827458664link w/ 2 Good: 25688220 Bad: 413212733628656488 link w/ 4 Good: 26086680 Bad: 41013204323918260703no link Good: 25603563 Bad: 41496323no link Good: 25740956 Bad: 413589325498977272 no link Good: 26126836 Bad: 41063447no link Good: 25278245 Bad: 4191203943134547151link w/ 3 Good: 25780618 Bad: 414096698763163066 4591813476195970847106132061936no link Good: 25799133 Bad: 41481549709764638080 741579691632289720481788874282334link w/ 3 Good: 25826875 Bad: 41544202271979644 9325526821540621120850706989754483no link Good: 25845459 Bad: 416160145473072988 23903128138559766272link w/ 1 Good: 25752259 Bad: 41799611link w/ 3 Good: 25890916 Bad: 416609557663629292 link w/ 4 Good: 26292181 Bad: 41350076link w/ 1 Good: 25437896 Bad: 42204362no link Good: 25804959 Bad: 41837300no link Good: 25943720 Bad: 4169854098979666 no link Good: 26311835 Bad: 41420824no link Good: 25455947 Bad: 42276713link w/ 2 Good: 25823683 Bad: 41908979626177700468281883082930003000 link w/ 2 Good: 26332831 Bad: 41490225link w/ 3 Good: 25475569 Bad: 423474884394679112link w/ 2 Good: 25983054 Bad: 4184000543636244 858925275595279148553no link Good: 25896579 Bad: 42016874no link Good: 26035876 Bad: 4187757876969588 no link Good: 26425767 Bad: 41578080no link Good: 25566600 Bad: 4243724993579268058link w/ 3 Good: 26075184 Bad: 41928667989299281212 449106493348413751010854030140216293697200055191907626166 link w/ 3 Good: 26484104 Bad: 41700534link w/ 3 Good: 25622440 Bad: 42562199link w/ 2 Good: 25992617 Bad: 421920243132542521004395942020 no link Good: 26537198 Bad: 4173783847478600257no link Good: 26045328 Bad: 42229710no link Good: 26185297 Bad: 42089742655029502844 6342802006no link Good: 25699493 Bad: 4266594270749468921086015457787626188 82452733757170273880588957366873link w/ 2 Good: 26229477 Bad: 42226354801800895943232 [?1049l [?1l>Caught SIGINT. Exiting... ]0;root@node1-1.sb9.orbit-lab.org: ~root@node1-1:~# ~netfpga/netfpga/projects/selftest/sw/selftest -cn ~netfpga/netfpga/projects/selftest/sw/selftest -cn Found net device: nf2c0 CPCI Information ---------------- Version: 4 (rev 1) Device (Virtex) Information --------------------------- Project directory: selftest Project name: Selftest Project description: NetFPGA selftest -- exercises all major subsystems of the board Device ID: 5 Version: 1.1.0 Built against CPCI version: 4 (rev 1) [?1049h(B[?7h(B NetFPGA selftest v1.00 alpha (BClock test: pass Reg test: pass MDIO test: pass Phy 1: rev 1 up, 1000Base-TX full Phy 2: rev 1 up, 1000Base-TX full Phy 3: rev 1 up, 1000Base-TX full Phy 4: rev 1 up, 1000Base-TX full PHY test: fail Port 1: no link Good: 3721 Bad: 13609 Port 2: no link Good: 3394 Bad: 13937 Port 3: no link Good: 3594 Bad: 13738 Port 4: no link Good: 3536 Bad: 13798 DRAM test: Iteration: 1 Good: 0 Bad: 0 B/W: nan Gbps SRAM test: Iteration: 1 Good: 0 Bad: 0 B/W: nan Gbps SATA Test Disabled DMA test: Iteration(one pkt write, read, compare): 40 Good: 40 Bad: 0 (BQ(B Quit 5088 Bad: 72862link w/ 4 Good: 33537 Bad: 744144127 Bad: 738254493 Bad: 734603210.74 Gbps34 Good: 33 Bad: 0 B/W: 4.43 Gbps88 88099110223858381124858679111527link w/ 1 Good: 87247 Bad: 111079653.426766120 Good: 120 Bad: 0 link w/ 2 Good: 132095 Bad: 156615128944 Bad: 159767link w/ 4 Good: 130310 Bad: 1584023130851 Bad: 157862879.40 Gbps100 Good: 99 Bad: 0 B/W: 3.32 Gbps66 4852029390no link Good: 181281 Bad: 19782728297396136836929541810 Good: 9 Bad: 0 B/W: 9.66 Gbps34133 Bad: 0 B/W: 3.57 Gbps2020 no link Good: 212477 Bad: 257027link w/ 3 Good: 207143 Bad: 262362420944260063121026925923312 Bad: 0 B/W: 10.74 Gbps67667144 315832831324677335224no link Good: 227758 Bad: 332144no link Good: 228736 Bad: 33116854200998288 8335266944no link Good: 275753 Bad: 3745447919071109link w/ 2 Good: 280313 Bad: 369987763323293232 33538405310326941374033073740995813319384087582091.3366659566 5450376586link w/ 1 Good: 344666 Bad: 486424link w/ 1 Good: 348904 Bad: 48218725037480712212799984.004040 link w/ 3 Good: 386112 Bad: 5353717509054639no link Good: 379808 Bad: 541677no link Good: 381557 Bad: 5399295471332331444 no link Good: 439241 Bad: 572640no link Good: 427410 Bad: 584472link w/ 4 Good: 432449 Bad: 579434link w/ 3 Good: 434275 Bad: 577609760.7466653.7788 link w/ 4 Good: 473152 Bad: 629121599026423no link Good: 465465 Bad: 6368106757763469989998825252 no link Good: 492259 Bad: 700413775287151458375708919no link Good: 486064 Bad: 70661132311.10432431666 53753845530link w/ 3 Good: 521795 Bad: 761275link w/ 2 Good: 528541 Bad: 754530link w/ 1 Good: 531077 Bad: 7519954307656496060 link w/ 3 Good: 590655 Bad: 782808no link Good: 574104 Bad: 799360no link Good: 581271 Bad: 7921942838518961665598979244 26107168531449269287116960047986338no link Good: 603316 Bad: 8605489833531530588 no link Good: 631255 Bad: 923003link w/ 1 Good: 611772 Bad: 942487201459341152329993096241400646387272 link w/ 4 Good: 684350 Bad: 96030136410680546link w/ 1 Good: 672799 Bad: 971854link w/ 3 Good: 676057 Bad: 968598435498974.0166 no link Good: 724720 Bad: 101032747033601031688no link Good: 712552 Bad: 1022497no link Good: 715925 Bad: 101912565063163038080 4388781560no link Good: 721026 Bad: 110442230789946613456490887870.9764633.8744 link w/ 3 Good: 782630 Bad: 11332125870357140link w/ 2 Good: 768902 Bad: 1146943link w/ 2 Good: 772929 Bad: 114291751501.189796988 283568770551link w/ 1 Good: 811056 Bad: 1195183182163984601382566680576327730729919292 no link Good: 862236 Bad: 1234401no link Good: 836369 Bad: 1260269no link Good: 847655 Bad: 1248984no link Good: 851801 Bad: 12448395456362366 813203057075403533299465830321200link w/ 2 Good: 870334 Bad: 13166978733969551000 Good: 1000 Bad: 0 link w/ 2 Good: 933727 Bad: 134369890567871749link w/ 4 Good: 917859 Bad: 13595691922515491560918308297 44 no link Good: 985970 Bad: 138185257002410821no link Good: 969580 Bad: 1398244no link Good: 974347 Bad: 13934783624863629 88 1005055 Bad: 1453163745398368087844703809289446532754596954.001212 37219511391005494 Bad: 15431191019346 Bad: 15292691024696 Bad: 15239207639299282 66 link w/ 2 Good: 1090338 Bad: 1548672link w/ 3 Good: 1057858 Bad: 15811537197267040775161497709262613.912020 13434695061no link Good: 1100969 Bad: 1628439link w/ 2 Good: 1115498 Bad: 1613911link w/ 3 Good: 1121130 Bad: 1608280271195942 44 no link Good: 1187460 Bad: 1632344link w/ 3 Good: 1153279 Bad: 16665266820651600173865459424301028 Good: 1027 Bad: 0 B/W: 3.94 Gbps88 link w/ 4 Good: 1213908 Bad: 1696292no link Good: 1178288 Bad: 1731913no link Good: 1193732 Bad: 1716470no link Good: 1199625 Bad: 17105787633626163232 no link Good: 1233021 Bad: 1767572link w/ 1 Good: 1195860 Bad: 180473421185887432181824719829594766 link w/ 2 Good: 1285709 Bad: 1805283324785243141link w/ 4 Good: 1264213 Bad: 18267817067382032282814412812784040 no link Good: 1336684 Bad: 1844704no link Good: 1298085 Bad: 188330431478466607321286601064336160944 5587091591link w/ 4 Good: 1315707 Bad: 1956078no link Good: 1333066 Bad: 1938720link w/ 1 Good: 1339791 Bad: 193199665194934.0088 8826173912no link Good: 1346969 Bad: 2015205link w/ 1 Good: 1364811 Bad: 199736527178903985222722615252 link w/ 3 Good: 1441398 Bad: 2011178link w/ 3 Good: 1399322 Bad: 20532552417502035077no link Good: 1424551 Bad: 202802891902460593.9366 7431468654431051119214496779329568986084323949346060 no link Good: 1493427 Bad: 2139938no link Good: 1448807 Bad: 2184559no link Good: 1467935 Bad: 21654327535415801653327326544 53954284224link w/ 1 Good: 1494211 Bad: 22295565136422101265211712025988726059788 link w/ 4 Good: 1592614 Bad: 222154245465626759566337478217394440215101 Good: 100 Bad: 0 B/W: 11.42 Gbps939287272 no link Good: 1611722 Bad: 2292834364191340366846363199239251231204832142642566 331133618398417441078060523089725link w/ 3 Good: 1613225 Bad: 23817315439595898080 8625099098no link Good: 1636538 Bad: 2448811link w/ 2 Good: 1657912 Bad: 242743926601341933987492914.0044 7258244499217501500728968397890no link Good: 1704909 Bad: 24708401097526525188 44861521280link w/ 3 Good: 1692597 Bad: 2573545no link Good: 1715128 Bad: 2551015link w/ 3 Good: 1723365 Bad: 25427792112459583.959292 link w/ 2 Good: 1784488 Bad: 25720474731186625350link w/ 2 Good: 1754193 Bad: 260234562582939575433929166 no link Good: 1837528 Bad: 2609405no link Good: 1783554 Bad: 2663380no link Good: 1806876 Bad: 26400592815359631577626256246200200 634077392380792772940431873705460no link Good: 1840566 Bad: 2696768209415857744 link w/ 3 Good: 1882828 Bad: 2744897link w/ 3 Good: 1825790 Bad: 2801936link w/ 1 Good: 1850424 Bad: 2777303link w/ 3 Good: 1859352 Bad: 276837722109190888 no link Good: 1935844 Bad: 2782276no link Good: 1878157 Bad: 2839964no link Good: 1903065 Bad: 2815057no link Good: 1912143 Bad: 2805980433972472391212 link w/ 4 Good: 1986474 Bad: 2822044927899806205311155410link w/ 2 Good: 1962357 Bad: 2846165764758574.0066 no link Good: 2005754 Bad: 28931594553095338471339927576no link Good: 1980933 Bad: 291798498591902020 38786950524link w/ 4 Good: 1977443 Bad: 3011868link w/ 2 Good: 2003775 Bad: 2985537link w/ 1 Good: 2013598 Bad: 2975715323153824823144 link w/ 2 Good: 2091886 Bad: 2987821no link Good: 2029745 Bad: 3049963no link Good: 2056338 Bad: 302337166442301326943357563.9588 [?1049l [?1l>Caught SIGINT. Exiting... ]0;root@node1-1.sb9.orbit-lab.org: ~root@node1-1:~# ]0;root@node1-1.sb9.orbit-lab.org: ~root@node1-1:~# ]0;root@node1-1.sb9.orbit-lab.org: ~root@node1-1:~# exit logout ]0;netfpga@node1-1: ~/netfpga/projects/selftest/swnetfpga@node1-1:~/netfpga/projects/selftest/sw$ ls bad_pkt_dump or_ip.c or_utils.o selftest_clk.o selftest_dram.h selftest_mdio.o selftest_reg.c selftest_serial.o bad_pkt_dump.c or_ip.h selftest selftest_dma.c selftest_dram.o selftest.o selftest_reg.h selftest_sram.c bad_pkt_dump.o or_ip.o selftest.c selftest_dma.h selftest.h selftest_phy.c selftest_reg.o selftest_sram.h Makefile or_utils.c selftest_clk.c selftest_dma.o selftest_mdio.c selftest_phy.h selftest_serial.c selftest_sram.o or_data_types.h or_utils.h selftest_clk.h selftest_dram.c selftest_mdio.h selftest_phy.o selftest_serial.h ]0;netfpga@node1-1: ~/netfpga/projects/selftest/swnetfpga@node1-1:~/netfpga/projects/selftest/sw$ lssudo su - ]0;root@node1-1.sb9.orbit-lab.org: ~root@node1-1:~# exit~netfpga/netfpga/projects/selftest/sw/selftest -cn Found net device: nf2c0 CPCI Information ---------------- Version: 4 (rev 1) Device (Virtex) Information --------------------------- Project directory: selftest Project name: Selftest Project description: NetFPGA selftest -- exercises all major subsystems of the board Device ID: 5 Version: 1.1.0 Built against CPCI version: 4 (rev 1) [?1049h(B[?7h(B NetFPGA selftest v1.00 alpha (BClock test: pass Reg test: pass MDIO test: pass Phy 1: rev 1 up, 1000Base-TX full Phy 2: rev 1 up, 1000Base-TX full Phy 3: rev 1 up, 1000Base-TX full Phy 4: rev 1 up, 1000Base-TX full PHY test: fail Port 1: link w/ 3 Good: 10183 Bad: 7138 Port 2: no link Good: 10063 Bad: 7259 Port 3: link w/ 2 Good: 10089 Bad: 7234 Port 4: link w/ 3 Good: 10135 Bad: 7189 DRAM test: Iteration: 1 Good: 0 Bad: 0 B/W: nan Gbps SRAM test: Iteration: 1 Good: 0 Bad: 0 B/W: nan Gbps SATA Test Disabled DMA test: Iteration(one pkt write, read, compare): 40 Good: 40 Bad: 0 (BQ(B Quit no link Good: 49136 Bad: 587844780160120no link Good: 48346 Bad: 59577no link Good: 48614 Bad: 59309325.37 Gbps34 Good: 33 Bad: 0 B/W: 2.21 Gbps88 68287130007654841328116653813175867169131128658.95676695 120 Good: 120 Bad: 0 113078 Bad: 175605link w/ 4 Good: 109381 Bad: 179303110744 Bad: 177941111632 Bad: 177054879.40100 Good: 99 Bad: 0 B/W: 3.32 Gbps66 link w/ 3 Good: 166208 Bad: 21287061678217401634322156486440821467310 Good: 9 Bad: 0 B/W: 9.66 Gbps34133 Bad: 0 B/W: 3.57 Gbps2020 no link Good: 186837 Bad: 282636no link Good: 180747 Bad: 28872783193862828435385124312 Bad: 0 B/W: 10.74 Gbps67667144 21139348477link w/ 1 Good: 203948 Bad: 35592820694835292920838535149354200998288 link w/ 3 Good: 264494 Bad: 385775no link Good: 256302 Bad: 3939685961190660link w/ 2 Good: 261215 Bad: 389057763323293232 3053394353196036444620link w/ 1 Good: 299907 Bad: 4407501301541439112091.3366659566 224537506521link w/ 4 Good: 313645 Bad: 517414no link Good: 318060 Bad: 513000no link Good: 320030 Bad: 5110312212799984.004040 45841963038146383750765124670214link w/ 2 Good: 353473 Bad: 567988540.743323313.7 44 3411538600314no link Good: 398702 Bad: 61315140396079093406249605607766665788 2386226362542446977779link w/ 2 Good: 430295 Bad: 671955no link Good: 432760 Bad: 669491989998825252 no link Good: 457748 Bad: 73489441978750666no link Good: 448500 Bad: 7441455127274137432311.10432431666 link w/ 4 Good: 509687 Bad: 773352link w/ 1 Good: 493117 Bad: 789923500014830275029800714307656496060 no link Good: 557055 Bad: 816380no link Good: 539699 Bad: 833737link w/ 1 Good: 546913 Bad: 8265244992482351465598979244 7622287608link w/ 3 Good: 557364 Bad: 906467no link Good: 565119 Bad: 89871468341954939833531530588 link w/ 4 Good: 607985 Bad: 946242no link Good: 587869 Bad: 966360961789580529957595465641400646387272 36113483488link w/ 1 Good: 640146 Bad: 1004478648839578765239792229435498974.0166 no link Good: 699249 Bad: 1035771no link Good: 677260 Bad: 1057761864041048618901391044884650.986316303.848080 71847110694494883130533link w/ 2 Good: 704670 Bad: 1120748link w/ 1 Good: 708549 Bad: 11168708776463744 link w/ 2 Good: 763882 Bad: 115193073938576428no link Good: 749620 Bad: 11661942535626225351501.189796988 no link Good: 808710 Bad: 11974988326822294193992212219no link Good: 797974 Bad: 1208238327730729919292 link w/ 4 Good: 860858 Bad: 123574783478461822link w/ 1 Good: 845828 Bad: 1250780link w/ 2 Good: 849930 Bad: 12466795456362366 no link Good: 907955 Bad: 127904781050305953no link Good: 892412 Bad: 1294592no link Good: 896645 Bad: 12903608733969551000 Good: 1000 Bad: 0 link w/ 4 Good: 927149 Bad: 1350247986927870591071936668091518836221260918308297 44 25910408685link w/ 4 Good: 929493 Bad: 1438302link w/ 4 Good: 942010 Bad: 1425786link w/ 3 Good: 946746 Bad: 14210513624863629 88 no link Good: 1012165 Bad: 1446021no link Good: 981837 Bad: 1476350no link Good: 994651 Bad: 1463538no link Good: 999581 Bad: 145860954596954.001212 link w/ 4 Good: 1051006 Bad: 14975801019501 Bad: 15290861032770 Bad: 15158181037938 Bad: 151065176079299283.89 66 no link Good: 1070090 Bad: 15688913702760195551049879355641682569709236261912020 115704613674link w/ 3 Good: 1081838 Bad: 164754196242633138link w/ 2 Good: 1101700 Bad: 1627681271195942 44 link w/ 2 Good: 1168753 Bad: 1651021113424185534link w/ 2 Good: 1148871 Bad: 1670905no link Good: 1154482 Bad: 16652954301028 Good: 1027 Bad: 0 B/W: 3.94 Gbps88 no link Good: 1188422 Bad: 1721750no link Good: 1152407 Bad: 1757766no link Good: 1167787 Bad: 1742388735367366397633626163232 link w/ 3 Good: 1213734 Bad: 1786833link w/ 3 Good: 1176612 Bad: 18239569250180806983888021839829594766 466753824209122900061963link w/ 1 Good: 1245141 Bad: 1845823251143981782814412812784040 no link Good: 1306723 Bad: 1874635no link Good: 1267889 Bad: 1913470no link Good: 1284528 Bad: 189683290576907854336160944 258399459185542862133028949688630909996265865194934.0088 603912001759318929204322236812025339link w/ 1 Good: 1343303 Bad: 201885198252272263.925252 link w/ 2 Good: 1413476 Bad: 2039072713481200link w/ 1 Good: 1389428 Bad: 20631233960856469919046059366 no link Good: 1439766 Bad: 2103175961146793no link Good: 1414939 Bad: 2128004no link Good: 1421698 Bad: 2121246323949346060 5890274436link w/ 4 Good: 1413786 Bad: 2219553331432001974015393189653327326544 51176521196916591257824link w/ 4 Good: 1485546 Bad: 223819192699231038726059788 link w/ 2 Good: 1558320 Bad: 2255809no link Good: 1511517 Bad: 23026131531557825755388375294101 Good: 100 Bad: 0 B/W: 11.42 Gbps939287272 no link Good: 1577459 Bad: 23270662922875298no link Good: 1549861 Bad: 23546665738834714032142642566 link w/ 3 Good: 1610118 Bad: 2384803link w/ 3 Good: 1560585 Bad: 243433781744413179link w/ 1 Good: 1589558 Bad: 24053675439595898080 no link Good: 1663153 Bad: 2422166no link Good: 1612920 Bad: 2472401link w/ 4 Good: 1634436 Bad: 245088636423804294387492914.0044 700271754424899852671770914504802no link Good: 1679042 Bad: 2496675109255265253.9488 19465466516660199512no link Good: 1689100 Bad: 2577014976035685122114595859292 6575890749link w/ 1 Good: 1711979 Bad: 2644530link w/ 2 Good: 1734887 Bad: 2621623link w/ 1 Good: 1743567 Bad: 26129445433929166 link w/ 2 Good: 1809810 Bad: 2637094no link Good: 1755012 Bad: 26918934783906851787101598077626256246200200 36288574416link w/ 4 Good: 1807356 Bad: 27299461831023706280no link Good: 1839825 Bad: 2697479209415857744 no link Good: 1909113 Bad: 271858235262775069no link Good: 1876737 Bad: 27509608557474212522109190888 2821589877no link Good: 1870267 Bad: 284782694982823113904175813921433972472391212 link w/ 3 Good: 1961054 Bad: 2847433901909906579link w/ 1 Good: 1927095 Bad: 2881395link w/ 3 Good: 1936612 Bad: 2871879764758574.0066 no link Good: 2014216 Bad: 2884669link w/ 4 Good: 1954215 Bad: 2944672279784919104no link Good: 1989408 Bad: 290948198591902020 5204937233no link Good: 1990972 Bad: 2998308201712172161link w/ 1 Good: 2026878 Bad: 29624053231348248233.9544 link w/ 2 Good: 2071111 Bad: 300856420087603070916no link Good: 2035381 Bad: 3044296no link Good: 2045301 Bad: 3034377433575688 no link Good: 2117613 Bad: 3052456link w/ 1 Good: 2054474 Bad: 3115597link w/ 2 Good: 2081438 Bad: 30886349148078593652908963232 link w/ 3 Good: 2170370 Bad: 3090099no link Good: 2106449 Bad: 315402111337921266791437941166799840923922766 48960316126024033226832no link Good: 2152060 Bad: 31988066227288595414039575684040 no link Good: 2216002 Bad: 3225254link w/ 3 Good: 2148980 Bad: 32922787754626371388096253164328908944 link w/ 4 Good: 2269087 Bad: 3262571no link Good: 2201333 Bad: 3330326link w/ 2 Good: 2230202 Bad: 330145824089890763654520232022988 308204313850link w/ 4 Good: 2239337 Bad: 3382718no link Good: 2268643 Bad: 33534137947734258087456554.005252 32732885121no link Good: 2257015 Bad: 3455435869642548997971414482515050898866 262804440040912795115663217381113link w/ 3 Good: 2333012 Bad: 346983632331221213.956060 34159167732334361149629link w/ 2 Good: 2374359 Bad: 351888385801507442545554644 no link Good: 2441302 Bad: 354233467650615987no link Good: 2398961 Bad: 35846772410583730578798988788 link w/ 2 Good: 2460998 Bad: 36130338600588024178846561491297376442960982222217272 351406250370link w/ 1 Good: 2438364 Bad: 37260707056993866no link Good: 2482555 Bad: 368188126175554866 no link Good: 2559595 Bad: 36952278311871705515676739148link w/ 2 Good: 2527690 Bad: 37271355443888798080 78782766438no link Good: 2500737 Bad: 3844484link w/ 2 Good: 2534048 Bad: 3811174no link Good: 2546205 Bad: 37990187632132044 612240823379329969026246687568746link w/ 2 Good: 2579207 Bad: 3856415709854534.0088 654060613link w/ 3 Good: 2585332 Bad: 3940683no link Good: 2619591 Bad: 39064251631998940192713387863.959292 701747914661no link Good: 2620444 Bad: 3995965553036110836782094859243421420666 link w/ 2 Good: 2720879 Bad: 3985928381084068700link w/ 2 Good: 2673724 Bad: 4033085286175402063576854537300300 no link Good: 2768061 Bad: 4029142link w/ 1 Good: 2684442 Bad: 4112762no link Good: 2720395 Bad: 4076811no link Good: 2733087 Bad: 406412098878644 8121067549no link Good: 2727485 Bad: 4160115link w/ 1 Good: 2763858 Bad: 4123743link w/ 2 Good: 2776611 Bad: 411099181807520519888 65152112845link w/ 1 Good: 2779831 Bad: 4198167281654961450382932048680434253521212 91047557912no link Good: 2824193 Bad: 4244196no link Good: 2861379 Bad: 4207011no link Good: 2874138 Bad: 4194253658685966 296712291144186731691979617916892692660909876196182020 link w/ 2 Good: 2963275 Bad: 4285910link w/ 4 Good: 2874578 Bad: 43746089126413365469260343231549190653524.0044 no link Good: 3016412 Bad: 43231663926934412645link w/ 1 Good: 2965372 Bad: 43742087875160831323386853.9688 524677513no link Good: 2961941 Bad: 4468035no link Good: 3000920 Bad: 4429057301430041567865871971873232 7164444872979563540811link w/ 2 Good: 3019211 Bad: 45011643284987527877525166 link w/ 4 Good: 3119034 Bad: 4491732link w/ 3 Good: 3026102 Bad: 45846661662544518798975308732009858484040 no link Good: 3171019 Bad: 4530145no link Good: 3077162 Bad: 4624003no link Good: 3117698 Bad: 4583468link w/ 3 Good: 3131423 Bad: 456974532024281881744 90173601388link w/ 4 Good: 3094766 Bad: 46967963598655575no link Good: 3149884 Bad: 4641680541515088 link w/ 4 Good: 3217245 Bad: 4664711no link Good: 3120653 Bad: 476130462489719469link w/ 2 Good: 3176543 Bad: 4705416876858495252 270346702005link w/ 3 Good: 3172961 Bad: 479939121519557158no link Good: 3229297 Bad: 474305710959189174.0066 30858754161no link Good: 3210029 Bad: 485272052750810000670749567211451506060 no link Good: 3327665 Bad: 4825480link w/ 1 Good: 3227749 Bad: 4925397710228212585570867578543884833.9644 64110794324628880654link w/ 2 Good: 3306731 Bad: 493681332150392204276730173016788 link w/ 4 Good: 3417219 Bad: 491671833151925018747no link Good: 3359369 Bad: 4974571link w/ 3 Good: 3374266 Bad: 495967598650497272 no link Good: 3441737 Bad: 49825943832486008830945041239no link Good: 3398074 Bad: 50262602221418382866 link w/ 2 Good: 3462343 Bad: 5052385157595157135link w/ 2 Good: 3402995 Bad: 5111736418118966144301171168080 45153978972740993895188556149512link w/ 3 Good: 3470926 Bad: 51342027655049944 no link Good: 3560188 Bad: 5135331no link Good: 3453708 Bad: 524181219980395719no link Good: 3515201 Bad: 5180322984838288 7932720658871327314590no link Good: 3518149 Bad: 526776933700252219313032162154.009292 613670626425046267168851777324538link w/ 2 Good: 3567564 Bad: 5308752438494866 link w/ 3 Good: 3666805 Bad: 52999035697840973160445162259162036246349653782813.97400400 2703106353995link w/ 4 Good: 3592150 Bad: 546495240190416913no link Good: 3656251 Bad: 5400853984131531444 no link Good: 3722087 Bad: 5425415no link Good: 3609847 Bad: 553765658435890697471472792414004948888 link w/ 2 Good: 3770029 Bad: 5467868link w/ 3 Good: 3657042 Bad: 5580856705989531911link w/ 2 Good: 3722407 Bad: 55154943282811212 no link Good: 3814045 Bad: 55142491700110628185link w/ 4 Good: 3749469 Bad: 5578827no link Good: 3766038 Bad: 556225965441541466 link w/ 4 Good: 3867124 Bad: 5551567no link Good: 3752464 Bad: 56662281802136616558188599837873484792020 no link Good: 3911610 Bad: 559747895977713113no link Good: 3845993 Bad: 56630986284646244509818044 link w/ 4 Good: 3930728 Bad: 56687548136108587643117351738129771818935275145134.0088 265287724590link w/ 3 Good: 3847068 Bad: 5842811link w/ 4 Good: 3898317 Bad: 5791563link w/ 1 Good: 3915483 Bad: 577439854647463232 40183466192819938780888no link Good: 3950983 Bad: 58292936828081199787081803.9766 453647817021no link Good: 3933384 Bad: 59372858562485046no link Good: 4003063 Bad: 58676086096146134040 no link Good: 4072713 Bad: 58883535106560100024003930957138link w/ 2 Good: 4021602 Bad: 5939468261394746844 link w/ 3 Good: 4121007 Bad: 5930456link w/ 4 Good: 3998603 Bad: 6052861link w/ 4 Good: 4051770 Bad: 5999695369649818175443807988 no link Good: 4171971 Bad: 5969888no link Good: 4048742 Bad: 60931181023346039528no link Good: 4120260 Bad: 602160376271371295252 910646041193link w/ 4 Good: 4066286 Bad: 6165972no link Good: 4120632 Bad: 611162738629364098464566 link w/ 3 Good: 4219178 Bad: 6103475393169229485478957476066271563867271679786060 7228740763414548467567link w/ 4 Good: 4200554 Bad: 6212499link w/ 2 Good: 4219090 Bad: 61939644358138124.0044 no link Good: 4309545 Bad: 6193901381597321850no link Good: 4237228 Bad: 6266220355854247595769464588 2873265104no link Good: 4199260 Bad: 63945805554233829917422231962198379783.977272 link w/ 2 Good: 4365987 Bad: 6318251link w/ 1 Good: 4235408 Bad: 6448831link w/ 4 Good: 4292224 Bad: 63920162311147730948180912911866 no link Good: 4419026 Bad: 6355607no link Good: 4287766 Bad: 6486868234493242970416393410700434245448080 link w/ 2 Good: 4442736 Bad: 6422294link w/ 3 Good: 4309968 Bad: 6555063no link Good: 4367786 Bad: 6497247no link Good: 4386919 Bad: 647811565787744 no link Good: 4464213 Bad: 6491209no link Good: 4329992 Bad: 6625431link w/ 4 Good: 4388468 Bad: 6566957link w/ 2 Good: 4407908 Bad: 654751887140114010988 517305528516link w/ 4 Good: 4382298 Bad: 6663525no link Good: 4441135 Bad: 6604689160736850899190545449292 link w/ 4 Good: 4561251 Bad: 65749664251727110468448751732no link Good: 4504211 Bad: 6632009324787766 no link Good: 4580382 Bad: 664623234280883807502800723816227007039176581111104.00500500 link w/ 4 Good: 4615500 Bad: 67015087689840111link w/ 2 Good: 4537339 Bad: 67796715751859493877444344 no link Good: 4668621 Bad: 6738781no link Good: 4529240 Bad: 687816390028173766102899711730093877763.9888 link w/ 4 Good: 4704037 Bad: 6793765link w/ 4 Good: 4563540 Bad: 6934264no link Good: 4624816 Bad: 6872989450788527283302422102091212 no link Good: 4723248 Bad: 6864946no link Good: 4581146 Bad: 700705043047945150link w/ 2 Good: 4663496 Bad: 6924702541444366 link w/ 4 Good: 4772136 Bad: 690645662923249361link w/ 2 Good: 4691487 Bad: 69871087121596643776777692020 38161525283872244967477349507034042no link Good: 4755690 Bad: 7013303109431030944 no link Good: 4869231 Bad: 6990154link w/ 4 Good: 4724564 Bad: 71348231876127177680846250927211434288 9129267036849no link Good: 4767104 Bad: 7182672no link Good: 4830621 Bad: 7119156516489813154776753232 3206710810link w/ 4 Good: 4784829 Bad: 72553484890091278link w/ 1 Good: 4870225 Bad: 71699547664094084.0066 6766262911no link Good: 4819220 Bad: 73113558374246836no link Good: 4905244 Bad: 72253339842414040 50207982001677159749369link w/ 4 Good: 4936425 Bad: 7284543link w/ 2 Good: 4958027 Bad: 72629412221176753.9844 552005616890476940659no link Good: 4970136 Bad: 7341234no link Good: 4991859 Bad: 73195124350950888 743423274192245793038846041330350104379132765042415252 12348668674link w/ 4 Good: 4970894 Bad: 7521268link w/ 2 Good: 5037252 Bad: 7454911593194328459837574966 73629408925no link Good: 5020120 Bad: 7562436no link Good: 5086888 Bad: 7495669link w/ 1 Good: 5109046 Bad: 747351231306086076060 9273780213774863520105169567786no link Good: 5127555 Bad: 7545401436414044 link w/ 4 Good: 5221533 Bad: 7541816link w/ 4 Good: 5065410 Bad: 76979403337562997link w/ 2 Good: 5155991 Bad: 760736165747388 no link Good: 5274663 Bad: 7579078no link Good: 5117763 Bad: 77359798609467649320881449348757087074.007272 link w/ 4 Good: 5311099 Bad: 76330425299291150link w/ 4 Good: 5221829 Bad: 7722315no link Good: 5244660 Bad: 769948541408414066 no link Good: 5330206 Bad: 77043297058863954no link Good: 5240063 Bad: 77944746309877144032074733.988080 [?1049l [?1l>Caught SIGINT. Exiting... ]0;root@node1-1.sb9.orbit-lab.org: ~root@node1-1:~# ~netfpga/netfpga/projects/selftest/sw/selftest -cn Found net device: nf2c0 CPCI Information ---------------- Version: 4 (rev 1) Device (Virtex) Information --------------------------- Project directory: selftest Project name: Selftest Project description: NetFPGA selftest -- exercises all major subsystems of the board Device ID: 5 Version: 1.1.0 Built against CPCI version: 4 (rev 1) [?1049h(B[?7h(B NetFPGA selftest v1.00 alpha (BClock test: pass Reg test: pass MDIO test: pass Phy 1: rev 1 up, 1000Base-TX full Phy 2: rev 1 up, 1000Base-TX full Phy 3: rev 1 up, 1000Base-TX full Phy 4: rev 1 up, 1000Base-TX full PHY test: fail Port 1: no link Good: 4243 Bad: 13088 Port 2: no link Good: 0 Bad: 0 Port 3: no link Good: 3229 Bad: 14106 Port 4: link w/ 3 Good: 2766 Bad: 14570 DRAM test: Iteration: 1 Good: 0 Bad: 0 B/W: nan Gbps SRAM test: Iteration: 1 Good: 0 Bad: 0 B/W: nan Gbps SATA Test Disabled DMA test: Iteration(one pkt write, read, compare): 40 Good: 40 Bad: 0 (BQ(B Quit 26409 Bad: 8151720490 Bad: 87439no link Good: 18031 Bad: 898993210.74 Gbps34 Good: 33 Bad: 0 B/W: 4.43 Gbps88 6723713105626034137956link w/ 3 Good: 51095 Bad: 147202658.95 Gbps67662.95 120 Good: 120 Bad: 0 link w/ 3 Good: 112340 Bad: 176342105383 Bad: 183302no link Good: 96400 Bad: 192285879.40100 Good: 99 Bad: 0 B/W: 3.32 Gbps66 no link Good: 134439 Bad: 244640link w/ 1 Good: 122576 Bad: 256506link w/ 3 Good: 118856 Bad: 26022710 Good: 9 Bad: 0 B/W: 9.66 Gbps34133 Bad: 0 B/W: 3.57 Gbps2020 615113079634no link Good: 145323 Bad: 32415334358335119312 Bad: 0 B/W: 10.74 Gbps67667144 link w/ 4 Good: 206815 Bad: 353056link w/ 1 Good: 190618 Bad: 369255no link Good: 179278 Bad: 38059654200998288 345590404671no link Good: 227742 Bad: 422521218735431530763323293232 no link Good: 267676 Bad: 472984link w/ 1 Good: 244685 Bad: 495978351985054662091.3366659566 3040155270416479234551825link w/ 3 Good: 262555 Bad: 5685052212799984.004040 link w/ 3 Good: 349323 Bad: 572131no link Good: 324530 Bad: 5969263078596135995471332331444 no link Good: 375703 Bad: 636144link w/ 4 Good: 347063 Bad: 664787no link Good: 335917 Bad: 675934760.7466653.7788 98187040628no link Good: 364460 Bad: 73778751720750528989998825252 44350849136link w/ 1 Good: 409768 Bad: 78287990988016632311.10432431666 8370699333no link Good: 448899 Bad: 834143436289467534307656496060 50577186766465893907545link w/ 3 Good: 452439 Bad: 92100065598979244 37230926601109404769786no link Good: 483362 Bad: 9804729833531530588 link w/ 3 Good: 559278 Bad: 9949495110551043175link w/ 1 Good: 499112 Bad: 105511941400646387272 9585410487712link w/ 1 Good: 546040 Bad: 10985873526723117905435498974.0166 64119386691334143688no link Good: 572029 Bad: 116299465063163038080 no link Good: 667268 Bad: 115814646139312114859977225638870.9764633.8744 898692259434131606842096155030030651501.189796988 link w/ 4 Good: 735171 Bad: 1271040no link Good: 676899 Bad: 1329314549251285327730729919292 no link Good: 775181 Bad: 1321422link w/ 1 Good: 715758 Bad: 1380848link w/ 3 Good: 700185 Bad: 13964225456362366 9713089869no link Good: 732666 Bad: 1454335no link Good: 716195 Bad: 14708078733969551000 Good: 1000 Bad: 0 8253774520136link w/ 4 Good: 757511 Bad: 15198813789053950360918308297 44 link w/ 3 Good: 870693 Bad: 1497099no link Good: 802815 Bad: 15649798321845853624863629 88 4901280556908299496282428165664163254596954.001212 no link Good: 923358 Bad: 16252204701770156332609715977639299282 66 link w/ 3 Good: 964837 Bad: 16741428link w/ 1 Good: 887451 Bad: 17515306628572697709262613.912020 no link Good: 1009316 Bad: 1720059no link Good: 931757 Bad: 1797620911604817773271195942 44 313178845648309871466328714301028 Good: 1027 Bad: 0 B/W: 3.94 Gbps88 link w/ 3 Good: 1058841 Bad: 185132720link w/ 1 Good: 971899 Bad: 1938271link w/ 3 Good: 948658 Bad: 19615147633626163232 no link Good: 1104153 Bad: 1896410no link Good: 1017205 Bad: 1983360no link Good: 993979 Bad: 20065879829594766 4223694872353652037306link w/ 1 Good: 1033060 Bad: 205790382814412812784040 64295201705971408109948no link Good: 1049237 Bad: 21321214336160944 2012287052121064726527977601941565194934.0088 4653411561251781210368link w/ 3 Good: 1122907 Bad: 223924398252272263.925252 link w/ 3 Good: 1272340 Bad: 21802037354079005no link Good: 1149949 Bad: 2302598919046059366 95515247428491629351316link w/ 1 Good: 1165544 Bad: 2377401323949346060 no link Good: 1340845 Bad: 229249223693496403205679427662653327326544 804603432775181448553no link Good: 1250383 Bad: 24733528726059788 402507411624link w/ 1 Good: 1292609 Bad: 252152565704548431101 Good: 100 Bad: 0 B/W: 11.42 Gbps939287272 33954705706321125834029640160812732142642566 link w/ 4 Good: 1456008 Bad: 2538913no link Good: 1338386 Bad: 2656537312099828255439595898080 39318392134873740711580link w/ 3 Good: 1340718 Bad: 274460387492914.0044 453848063723341904456671no link Good: 1386014 Bad: 2789703109255265253.9488 no link Good: 1564036 Bad: 2702073408258252864132258528872114595859292 link w/ 4 Good: 1587372 Bad: 2769136305929297218294199270915433929166 no link Good: 1632702 Bad: 281420050459794230770143767627626256246200200 link w/ 3 Good: 1672085 Bad: 28652124268094619link w/ 1 Good: 1514597 Bad: 3022703209415857744 no link Good: 1694101 Bad: 2933594592753068422no link Good: 1530489 Bad: 309720922109190888 722427956622link w/ 1 Good: 1583836 Bad: 3134256link w/ 3 Good: 1553103 Bad: 3164990433972472391212 6773304074962913779352no link Good: 1598415 Bad: 3210074764758574.0066 97805101077no link Good: 1655910 Bad: 32429756308266806098591902020 8198436943573186316094471103421713231348248233.9544 6187221780247145126516link w/ 3 Good: 1681667 Bad: 3398011433575688 9057886428658097411979726982443094652908963232 27926332535link w/ 1 Good: 1774609 Bad: 3485855no link Good: 1747950 Bad: 35125159840923922766 5613494731699183551686456786302414039575684040 200143643982384449596767link w/ 3 Good: 1809866 Bad: 3631397328908944 3885392801no link Good: 1880229 Bad: 3651428no link Good: 1848024 Bad: 3683634654520232022988 60938561112link w/ 1 Good: 1897459 Bad: 37245946312375893187456554.005252 985116139368no link Good: 1933466 Bad: 377898492061820390515050898866 14381359030787798240669373686547832331221213.956060 68892724346995193722link w/ 3 Good: 1963760 Bad: 3929482545554644 926139102340link w/ 1 Good: 2018664 Bad: 3964975no link Good: 1979878 Bad: 40037618798988788 link w/ 3 Good: 2237933 Bad: 3836101no link Good: 2063973 Bad: 401006320207795325860982222217272 no link Good: 2276945 Bad: 3887478link w/ 1 Good: 2101456 Bad: 4062970647369969126175554866 99101955721no link Good: 2118513 Bad: 4136312809211739055443888798080 331163401405824750977201112852339397632132044 531858242964572271045link w/ 1 Good: 2127354 Bad: 4308264709854534.0088 link w/ 4 Good: 2390898 Bad: 41351124link w/ 1 Good: 2201046 Bad: 43249663567156929827187869292 43620680201no link Good: 2246334 Bad: 4370075no link Good: 2202024 Bad: 441438743334214203.9666 no link Good: 2461087 Bad: 424571866293440514282867852276854537300300 851243120776link w/ 1 Good: 2285732 Bad: 4511472link w/ 1 Good: 2243550 Bad: 455365498878644 link w/ 3 Good: 2530431 Bad: 4357168no link Good: 2331020 Bad: 455658138437560322881807520519888 no link Good: 2569269 Bad: 440871968169609822no link Good: 2327948 Bad: 4650044434253521212 9133477054850158337644102724290658685966 62153153728link w/ 4 Good: 2411921 Bad: 4746867link w/ 3 Good: 2367548 Bad: 47912419876196182020 66839823401572249195no link Good: 2412876 Bad: 48363069190653524.0044 96270643307832158563654449395088325868588 718318711654no link Good: 2499898 Bad: 4930077link w/ 1 Good: 2459904 Bad: 497007265387197183.973232 609945937950542054783213949825025395877525166 80428806485link w/ 1 Good: 2584866 Bad: 5025906no link Good: 2540285 Bad: 50704872009858484040 2626874894no link Good: 2602058 Bad: 50991066024814091832024281881744 5506193649922716216440178570212994541515088 link w/ 4 Good: 2900359 Bad: 4981594link w/ 4 Good: 2672449 Bad: 520950662387758079876858495252 no link Good: 2937206 Bad: 5035143no link Good: 2707427 Bad: 52649256136231099110959189174.0066 5920210354225331337417687985868211451506060 97373557684link w/ 1 Good: 2761954 Bad: 5391189link w/ 3 Good: 2706909 Bad: 5446236549848344 link w/ 4 Good: 3042689 Bad: 5200849no link Good: 2807236 Bad: 5436304no link Good: 2752212 Bad: 54913307637301730163.9788 6720666731271185068217745755648398650497272 no link Good: 3091472 Bad: 533285964682077514929686313662221418382866 link w/ 4 Good: 3136796 Bad: 5377933921622611834434802994301171168080 no link Good: 3175210 Bad: 542991392879376333776297274987655049944 97147983714634274917993560801962984838288 link w/ 4 Good: 3229160 Bad: 55567578link w/ 4 Good: 2976101 Bad: 580981892385162070313032162154.009292 no link Good: 3251318 Bad: 5624997no link Good: 2993737 Bad: 588258039520936798438494866 89649770586030305809361369395973166578281400400 link w/ 4 Good: 3334951 Bad: 5722153link w/ 1 Good: 3075868 Bad: 5981238link w/ 3 Good: 3014707 Bad: 60424019813153143.9744 no link Good: 3359199 Bad: 57883024958556051649no link Good: 3040082 Bad: 6107423414004948888 link w/ 3 Good: 3383667 Bad: 58542362no link Good: 3115667 Bad: 612223856257816483282811212 no link Good: 3428966 Bad: 5899328link w/ 4 Good: 3160975 Bad: 6167322link w/ 3 Good: 3098094 Bad: 623020465441541466 67159951530no link Good: 3197470 Bad: 6221221no link Good: 3141064 Bad: 6277628873484792020 8932360197642147919429957401351690509818044 520082793984link w/ 1 Good: 3243150 Bad: 6356332link w/ 3 Good: 3181562 Bad: 641792135275145134.0088 link w/ 3 Good: 3565401 Bad: 6124479884634014192268716301254647463232 no link Good: 3594246 Bad: 6186027no link Good: 3314408 Bad: 6465867no link Good: 3258226 Bad: 65220508750818066 616264254406link w/ 1 Good: 3331352 Bad: 6539320link w/ 1 Good: 3274284 Bad: 659638960946146133.974040 59503015546no link Good: 3374253 Bad: 65868083310391650671261394746844 link w/ 3 Good: 3702190 Bad: 634927241645963500555709957565443807988 no link Good: 3724225 Bad: 6417636link w/ 4 Good: 3433751 Bad: 6708112no link Good: 3375353 Bad: 676651276271371295252 5357178684815964972608link w/ 3 Good: 3393874 Bad: 683838598464566 98875523777no link Good: 3504947 Bad: 6817707no link Good: 3439173 Bad: 68834837271679786060 83521377834395073543762779367744358138124.0044 57240646201link w/ 4 Good: 3556761 Bad: 6946682919557011489769464588 link w/ 4 Good: 3896020 Bad: 669781870no link Good: 3594390 Bad: 69994505224877135498879787272 no link Good: 3941319 Bad: 67429156397047044533link w/ 3 Good: 3567790 Bad: 71164488180399129113.9866 link w/ 3 Good: 3965263 Bad: 680936858966115668no link Good: 3593141 Bad: 7181494434245448080 [?1049l [?1l>]0;root@node1-1.sb9.orbit-lab.org: ~root@node1-1:~# lear No command 'lear' found, did you mean: Command 'klear' from package 'klear' (universe) Command 'leaf' from package 'cone' (universe) Command 'clear' from package 'ncurses-bin' (main) Command 'pear' from package 'php-pear' (main) lear: command not found ]0;root@node1-1.sb9.orbit-lab.org: ~root@node1-1:~# clear ]0;root@node1-1.sb9.orbit-lab.org: ~root@node1-1:~# clear ]0;root@node1-1.sb9.orbit-lab.org: ~root@node1-1:~# exit logout ]0;netfpga@node1-1: ~/netfpga/projects/selftest/swnetfpga@node1-1:~/netfpga/projects/selftest/sw$ pwd /home/netfpga/netfpga/projects/selftest/sw ]0;netfpga@node1-1: ~/netfpga/projects/selftest/swnetfpga@node1-1:~/netfpga/projects/selftest/sw$ ls bad_pkt_dump or_ip.c or_utils.o selftest_clk.o selftest_dram.h selftest_mdio.o selftest_reg.c selftest_serial.o bad_pkt_dump.c or_ip.h selftest selftest_dma.c selftest_dram.o selftest.o selftest_reg.h selftest_sram.c bad_pkt_dump.o or_ip.o selftest.c selftest_dma.h selftest.h selftest_phy.c selftest_reg.o selftest_sram.h Makefile or_utils.c selftest_clk.c selftest_dma.o selftest_mdio.c selftest_phy.h selftest_serial.c selftest_sram.o or_data_types.h or_utils.h selftest_clk.h selftest_dram.c selftest_mdio.h selftest_phy.o selftest_serial.h ]0;netfpga@node1-1: ~/netfpga/projects/selftest/swnetfpga@node1-1:~/netfpga/projects/selftest/sw$ cd ../ -bash: ../: is a directory ]0;netfpga@node1-1: ~/netfpga/projects/selftest/swnetfpga@node1-1:~/netfpga/projects/selftest/sw$ cd ../ ]0;netfpga@node1-1: ~/netfpga/projects/selftestnetfpga@node1-1:~/netfpga/projects/selftest$ ls include lib Makefile src sw synth verif ]0;netfpga@node1-1: ~/netfpga/projects/selftestnetfpga@node1-1:~/netfpga/projects/selftest$ cd src/ ]0;netfpga@node1-1: ~/netfpga/projects/selftest/srcnetfpga@node1-1:~/netfpga/projects/selftest/src$ ls aurora_framing_aurora_lane.v aurora_framing_rx_ll.v ddr2_test_reg.v phy_test_pktsrc.v serial_test.v aurora_framing_channel_error_detect.v aurora_framing_standard_cc_module.v ddr2_test.v phy_test_port_ctrl.v serial_tst_regs.v aurora_framing_channel_init_sm.v aurora_framing_sym_dec.v dump.v phy_test_port_grp.v small_async_fifo.v aurora_framing_chbond_count_dec.v aurora_framing_sym_gen.v lfsr32.v phy_test_reg.v sram_test_fast.v aurora_framing_error_detect.v aurora_framing_tx_ll_control.v nf2_core.v phy_test_rx_log_reg.v sram_test_fixed_pat_fast.v aurora_framing_frame_check.v aurora_framing_tx_ll_datapath.v nf2_mac_grp.v phy_test_rx_reg.v sram_test_fixed_pat.v aurora_framing_frame_gen.v aurora_framing_tx_ll.v nf2_rxfifo_sm.v phy_test_tx_reg.v sram_test_rand_pat_fast.v aurora_framing_global_logic.v aurora_framing.v nf2_sram_sm_fast.v phy_test.v sram_test_rand_pat.v aurora_framing_idle_and_ver_gen.v aurora_module.v nf2_sram_sm.v reg_addr_reflect.v sram_test_reg.v aurora_framing_lane_init_sm.v clk_test_reg.v nf2_top.v reg_file_test.v sram_test.v aurora_framing_phase_align.v cpu_dma_queue.v nf2_txfifo_sm.v reg_sram_msb.v testbench_inc.v aurora_framing_rx_ll_nfc.v dcmx3y0_2vp50.v phy_test_pktcmp.v rgmii_io.v unet_defines.v aurora_framing_rx_ll_pdu_datapath.v ddr2_dram_access_reg.v phy_test_pktgen.v selftest_result.v ]0;netfpga@node1-1: ~/netfpga/projects/selftest/srcnetfpga@node1-1:~/netfpga/projects/selftest/src$ vi less phy_test_pktgen.v [?1049h[?1h= /////////////////////////////////////////////////////////////////////////////// // vim:set shiftwidth=3 softtabstop=3 expandtab: // $Id: phy_test_pktgen.v 1794 2007-05-21 01:38:29Z grg $ // // Module: phy_test_pktgen.v // Project: NetFPGA // Description: Selftest module for Ethernet Phys. // // This particular module is responsible for generating packets // only. The packet format is as follows: // // DA: 00:ca:fe:00:01:Port // SA: 00:ca:fe:00:00:Port // Length: Length // Data: 8'b0, pattern (8 bits) // seq_no (or 0) // Pattern // // Note: data is muxed -- not the direct output for a flop // /////////////////////////////////////////////////////////////////////////////// module phy_test_pktgen #(parameter CPCI_NF2_DATA_WIDTH = 32, NUM_PATTERNS = 5, SEQ_NO_WIDTH = 32 ) ( output [31:0] data, output reg [3:0] ctrl, input rd_en, // Output the next word input [2:0] port, // Source port number input [NUM_PATTERNS - 1:0] pattern, // Pattern enable input [10:0] pkt_size, // Packet size input [SEQ_NO_WIDTH - 1:0] seq_no, // Initial sequence number output reg busy, // Currently transmitting packets output reg done, // Indicates the last word of the packet is being output //--- misc input reset, input clk phy_test_pktgen.v   ESCESCOOBB  ); :  ESCESCOOBB  :  ESCESCOOBB  // Identify different patters :  ESCESCOOBB  localparam ALL_0_PATTERN = 5'b00001; :  ESCESCOOBB  localparam ALL_1_PATTERN = 5'b00010; :  ESCESCOOBB  localparam ALT_01_PATTERN = 5'b00100; :  ESCESCOOBB  localparam ALT_10_PATTERN = 5'b01000; :  ESCESCOOBB  localparam RANDOM_PATTERN = 5'b10000; :  ESCESCOOBB  :  ESCESCOOBB  // Count when the LFSR should be enabled :  ESCESCOOBB  localparam START_LFSR = 'd5; :  ESCESCOOBB  :  ESCESCOOBB  // Word locations of various packet components :  ESCESCOOBB  localparam DA_HI = 'd0; :  ESCESCOOBB  localparam DA_LO_SA_HI = 'd1; :  ESCESCOOBB  localparam SA_LO = 'd2; :  ESCESCOOBB  localparam SIZE_PATTERN = 'd3; :  ESCESCOOBB  localparam SEQUENCE_NO = 'd4; :  ESCESCOOBB  :  ESCESCOOBB  // Packet length related variables :  ESCESCOOBB  reg [8:0] num_words; :  ESCESCOOBB  reg [3:0] final_ctrl; :  ESCESCOOBB  :  ESCESCOOBB  reg [8:0] count; :  ESCESCOOBB  :  ESCESCOOBB  wire [31:0] rand_data; :  ESCESCOOBB  reg [31:0] header_nxt; :  ESCESCOOBB  reg [31:0] payload; :  ESCESCOOBB  reg [31:0] header; :  ESCESCOOBB  :  ESCESCOOBB  reg done_nxt; :  ESCESCOOBB  wire last_word; :  ESCESCOOBB  :  ESCESCOOBB  reg enable_lfsr; :  ESCESCOOBB  :  ESCESCOOBB  reg sel_payload; :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  // ================================= :  ESCESCOOBB  // Main state machine responsible for packet transmission :  ESCESCOOBB  // Tracks the current word and places data on the output signals :  ESCESCOOBB  :  ESCESCOOBB  // Generate the last word signal :  ESCESCOOBB  assign last_word = count == num_words - 1; :  ESCESCOOBB  :  ESCESCOOBB  always @(posedge clk) :  ESCESCOOBB  begin :  ESCESCOOBB  // Track the count and calculate the data to send :  ESCESCOOBB  if (reset) begin :  ESCESCOOBB  count <= 'h0; :  ESCESCOOBB  enable_lfsr <= 1'b0; :  ESCESCOOBB  final_ctrl <= 4'b0000; :  ESCESCOOBB  num_words <= {9{1'b1}}; :  ESCESCOOBB  ctrl <= 'h0; :  ESCESCOOBB  done <= 1'b0; :  ESCESCOOBB  busy <= 1'b0; :  ESCESCOOBB  sel_payload <= 1'b0; :  ESCESCOOBB  header <= 'h0; :  ESCESCOOBB  end :  ESCESCOOBB  else if (rd_en) begin :  ESCESCOOBB  if (last_word) begin :  ESCESCOOBB  // If we are on the last word we should reset the :  ESCESCOOBB  // counter and move to the next pattern :  ESCESCOOBB  // :  ESCESCOOBB  // Don't reset the LFSR here as the output may not :  ESCESCOOBB  // have been processed yet :  ESCESCOOBB  count <= 'h0; :  ESCESCOOBB  final_ctrl <= 4'b0000; :  ESCESCOOBB  num_words <= {9{1'b1}}; :  ESCESCOOBB  ctrl <= final_ctrl; :  ESCESCOOBB  done <= 1'b1; :  ESCESCOOBB  sel_payload <= 1'b1; :  ESCESCOOBB  header <= header_nxt; :  ESCESCOOBB  end :  ESCESCOOBB  else begin :  ESCESCOOBB  // Record the size and pattern if we're :  ESCESCOOBB  // on the appropriate word :  ESCESCOOBB  if (count == SIZE_PATTERN) begin :  ESCESCOOBB  // Work out how many words we expect to send :  ESCESCOOBB  num_words <= pkt_size[10:2] + (|pkt_size[1:0]); :  ESCESCOOBB  :  ESCESCOOBB  // Calculate the control bits for the final word :  ESCESCOOBB  case (pkt_size[1:0]) :  ESCESCOOBB  2'd0 : final_ctrl <= 4'b0001; :  ESCESCOOBB  2'd1 : final_ctrl <= 4'b1000; :  ESCESCOOBB  2'd2 : final_ctrl <= 4'b0100; :  ESCESCOOBB  2'd3 : final_ctrl <= 4'b0010; :  ESCESCOOBB  endcase :  ESCESCOOBB  end :  ESCESCOOBB  :  ESCESCOOBB  // Enable the LFSR if appropriate :  ESCESCOOBB  if (count == START_LFSR) :  ESCESCOOBB  enable_lfsr <= 1'b1; :  ESCESCOOBB  else if (count == 'h0) :  ESCESCOOBB  enable_lfsr <= 1'b0; :  ESCESCOOBB  :  ESCESCOOBB  // If we are not on the last word then we should increment the :  ESCESCOOBB  // counter but don't touch the pattern :  ESCESCOOBB  count <= count + 'h1; :  ESCESCOOBB  header <= header_nxt; :  ESCESCOOBB  ctrl <= 'h0; :  ESCESCOOBB  done <= 1'b0; :  ESCESCOOBB  if (count == 'h0) :  ESCESCOOBB  sel_payload <= 1'b0; :  ESCESCOOBB  else if (count == SEQUENCE_NO) :  ESCESCOOBB  sel_payload <= 1'b1; :  ESCESCOOBB  end :  ESCESCOOBB  busy <= 1'b1; :  ESCESCOOBB  end :  ESCESCOOBB  else if (count == 'h0) :  ESCESCOOBB  busy <= 1'b0; :  ESCESCOOBB  end :  ESCESCOOBB  :  ESCESCOOBB  assign data = sel_payload ? payload : header; :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  // ================================= :  ESCESCOOBB  // Muxes to work out what data to transmit :  ESCESCOOBB  :  ESCESCOOBB  always @* :  ESCESCOOBB  begin :  ESCESCOOBB  case (count) :  ESCESCOOBB  //DA_HI : header_nxt = 32'h 00_ca_fe_00; :  ESCESCOOBB  DA_LO_SA_HI : header_nxt = {8'h 01, 5'd0, port, 16'h 00_ca}; :  ESCESCOOBB  SA_LO : header_nxt = {24'h fe_00_00, 5'd0, port}; :  ESCESCOOBB  SIZE_PATTERN: header_nxt = {4'hf, 1'b0, pkt_size, 8'd0, {(8 - NUM_PATTERNS){1'b0}}, pattern}; :  ESCESCOOBB  default : header_nxt = 32'h 00_ca_fe_00; :  ESCESCOOBB  endcase :  ESCESCOOBB  end :  ESCESCOOBB  :  ESCESCOOBB  always @* :  ESCESCOOBB  begin :  ESCESCOOBB  case (pattern) :  ESCESCOOBB  ALL_0_PATTERN : payload = 32'h 00000000; :  ESCESCOOBB  ALL_1_PATTERN : payload = 32'h ffffffff; :  ESCESCOOBB  ALT_01_PATTERN : payload = 32'h 55555555; :  ESCESCOOBB  ALT_10_PATTERN : payload = 32'h aaaaaaaa; :  ESCESCOOBB  default : payload = rand_data; :  ESCESCOOBB  endcase :  ESCESCOOBB  end :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  // ================================= :  ESCESCOOBB  // LFSR to generate random patterns :  ESCESCOOBB  // :  ESCESCOOBB  // The LFSR should only progress when we are generating a random pattern at :  ESCESCOOBB  // only when we are in the payload section. :  ESCESCOOBB  // :  ESCESCOOBB  // The first word should actually be repeated twice in the payload to allow :  ESCESCOOBB  // the receiver to start an identical LFSR :  ESCESCOOBB  lfsr32 patgen ( :  ESCESCOOBB  .val (rand_data), :  ESCESCOOBB  .rd (pattern == RANDOM_PATTERN && rd_en && enable_lfsr), :  ESCESCOOBB  .seed (seq_no), :  ESCESCOOBB  .reset (reset || !enable_lfsr), :  ESCESCOOBB  .clk (clk) :  ESCESCOOBB  ); :  ESCESCOOBB  :  ESCESCOOBB endmodule // phy_test_pktgen (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOAA M // =================================  :  ESCESCOOAA M  :  ESCESCOOAA M  :  ESCESCOOAA M  :  ESCESCOOAA M assign data = sel_payload ? payload : header;  :  ESCESCOOAA M  :  ESCESCOOAA M end  :  ESCESCOOAA M busy <= 1'b0;  :  ESCESCOOAA M else if (count == 'h0)  :  ESCESCOOAA M end  :  ESCESCOOAA M busy <= 1'b1;  :  ESCESCOOAA M end  :  ESCESCOOAA M sel_payload <= 1'b1;  :  ESCESCOOAA M else if (count == SEQUENCE_NO)  :  ESCESCOOAA M sel_payload <= 1'b0;  :  ESCESCOOAA M if (count == 'h0)  :  ESCESCOOAA M done <= 1'b0;  :  ESCESCOOAA M ctrl <= 'h0;  :  ESCESCOOAA M header <= header_nxt;  :  ESCESCOOAA M count <= count + 'h1;  :  ESCESCOOAA M // counter but don't touch the pattern  :  ESCESCOOAA M // If we are not on the last word then we should increment the  :  ESCESCOOAA M  :  ESCESCOOAA M enable_lfsr <= 1'b0;  :  ESCESCOOAA M else if (count == 'h0)  :  ESCESCOOAA M enable_lfsr <= 1'b1;  :  ESCESCOOAA M if (count == START_LFSR)  :  ESCESCOOAA M // Enable the LFSR if appropriate  :  ESCESCOOAA M  :  ESCESCOOAA M end  :  ESCESCOOAA M endcase  :  ESCESCOOAA M 2'd3 : final_ctrl <= 4'b0010;  :  ESCESCOOAA M 2'd2 : final_ctrl <= 4'b0100;  :  ESCESCOOAA M 2'd1 : final_ctrl <= 4'b1000;  :  ESCESCOOAA M 2'd0 : final_ctrl <= 4'b0001;  :  ESCESCOOAA M case (pkt_size[1:0])  :  ESCESCOOAA M // Calculate the control bits for the final word  :  ESCESCOOAA M  :  ESCESCOOAA M num_words <= pkt_size[10:2] + (|pkt_size[1:0]);  :  ESCESCOOAA M // Work out how many words we expect to send  :  ESCESCOOAA M if (count == SIZE_PATTERN) begin  :  ESCESCOOAA M // on the appropriate word  :  ESCESCOOAA M // Record the size and pattern if we're  :  ESCESCOOAA M else begin  :  ESCESCOOAA M end  :  ESCESCOOAA M header <= header_nxt;  :  ESCESCOOAA M sel_payload <= 1'b1;  :  ESCESCOOAA M done <= 1'b1;  :  ESCESCOOAA M ctrl <= final_ctrl;  :  ESCESCOOAA M num_words <= {9{1'b1}};  :  ESCESCOOAA M final_ctrl <= 4'b0000;  :  ESCESCOOAA M count <= 'h0;  :  ESCESCOOAA M // have been processed yet  :  ESCESCOOAA M // Don't reset the LFSR here as the output may not  :  ESCESCOOAA M //  :  ESCESCOOAA M // counter and move to the next pattern  :  ESCESCOOAA M // If we are on the last word we should reset the  :  ESCESCOOAA M if (last_word) begin  :  ESCESCOOAA M else if (rd_en) begin  :  ESCESCOOAA M end  :  ESCESCOOAA M header <= 'h0;  :  ESCESCOOAA M sel_payload <= 1'b0;  :  ESCESCOOAA M busy <= 1'b0;  :  ESCESCOOAA M done <= 1'b0;  :  ESCESCOOAA M ctrl <= 'h0;  :  ESCESCOOAA M num_words <= {9{1'b1}};  :  ESCESCOOAA M final_ctrl <= 4'b0000;  :  ESCESCOOAA M enable_lfsr <= 1'b0;  :  ESCESCOOAA M count <= 'h0;  :  ESCESCOOAA M if (reset) begin  :  ESCESCOOAA M // Track the count and calculate the data to send  :  ESCESCOOAA M begin  :  ESCESCOOAA M always @(posedge clk)  :  ESCESCOOAA M  :  ESCESCOOAA M assign last_word = count == num_words - 1;  :  ESCESCOOAA M // Generate the last word signal  :  ESCESCOOAA M  :  ESCESCOOAA M // Tracks the current word and places data on the output signals  :  ESCESCOOAA M // Main state machine responsible for packet transmission  :  ESCESCOOAA M // =================================  :  ESCESCOOAA M  :  ESCESCOOAA M  :  ESCESCOOAA M  :  ESCESCOOAA M reg sel_payload;  :  ESCESCOOAA M  :  ESCESCOOAA M reg enable_lfsr;  :  ESCESCOOAA M  :  ESCESCOOAA M wire last_word;  :  ESCESCOOAA M reg done_nxt;  :  ESCESCOOAA M  :  ESCESCOOAA M reg [31:0] header;  :  ESCESCOOAA M reg [31:0] payload;  :  ESCESCOOAA M reg [31:0] header_nxt;  :  ESCESCOOAA M wire [31:0] rand_data;  :  ESCESCOOAA M  :  ESCESCOOAA M reg [8:0] count;  :  ESCESCOOAA M  :  ESCESCOOAA M reg [3:0] final_ctrl;  :  ESCESCOOAA M reg [8:0] num_words;  :  ESCESCOOAA M // Packet length related variables  :  ESCESCOOAA M  :  ESCESCOOAA M localparam SEQUENCE_NO = 'd4;  :  ESCESCOOAA M localparam SIZE_PATTERN = 'd3;  :  ESCESCOOAA M localparam SA_LO = 'd2;  :  ESCESCOOAA M localparam DA_LO_SA_HI = 'd1;  :  ESCESCOOAA M localparam DA_HI = 'd0;  :  ESCESCOOAA M // Word locations of various packet components  :  ESCESCOOAA M  :  ESCESCOOAA M localparam START_LFSR = 'd5;  :  ESCESCOOAA M // Count when the LFSR should be enabled  :  ESCESCOOAA M  :  ESCESCOOAA M localparam RANDOM_PATTERN = 5'b10000;  :  ESCESCOOAA M localparam ALT_10_PATTERN = 5'b01000;  :  ESCESCOOAA M localparam ALT_01_PATTERN = 5'b00100;  :  ESCESCOOAA M localparam ALL_1_PATTERN = 5'b00010;  :  ESCESCOOAA M localparam ALL_0_PATTERN = 5'b00001;  :  ESCESCOOAA M // Identify different patters  :  ESCESCOOAA M  :  ESCESCOOAA M );  :  ESCESCOOAA M input clk  :  ESCESCOOAA M input reset,  :  ESCESCOOAA M //--- misc  :  ESCESCOOAA M  :  ESCESCOOAA M output reg done, // Indicates the last word of the packet is being output  :  ESCESCOOAA M output reg busy, // Currently transmitting packets  :  ESCESCOOAA M  :  ESCESCOOAA M input [SEQ_NO_WIDTH - 1:0] seq_no, // Initial sequence number  :  ESCESCOOAA M input [10:0] pkt_size, // Packet size  :  ESCESCOOAA M input [NUM_PATTERNS - 1:0] pattern, // Pattern enable  :  ESCESCOOAA M input [2:0] port, // Source port number  :  ESCESCOOAA M  :  ESCESCOOAA M input rd_en, // Output the next word  :  ESCESCOOAA M output reg [3:0] ctrl,  :  ESCESCOOAA M output [31:0] data,  :  ESCESCOOAA M (  :  ESCESCOOAA M )  :  ESCESCOOAA M SEQ_NO_WIDTH = 32  :  ESCESCOOAA M NUM_PATTERNS = 5,  :  ESCESCOOAA M CPCI_NF2_DATA_WIDTH = 32,  :  ESCESCOOAA Mmodule phy_test_pktgen #(parameter  :  ESCESCOOAA M  :  ESCESCOOAA M///////////////////////////////////////////////////////////////////////////////  :  ESCESCOOAA M//  :  ESCESCOOAA M// Note: data is muxed -- not the direct output for a flop  :  ESCESCOOAA M//  :  ESCESCOOAA M// Pattern  :  ESCESCOOAA M// seq_no (or 0)  :  ESCESCOOAA M// Data: 8'b0, pattern (8 bits)  :  ESCESCOOAA M// Length: Length  :  ESCESCOOAA M// SA: 00:ca:fe:00:00:Port  :  ESCESCOOAA M// DA: 00:ca:fe:00:01:Port  :  ESCESCOOAA M//  :  ESCESCOOAA M// only. The packet format is as follows:  :  ESCESCOOAA M// This particular module is responsible for generating packets  :  ESCESCOOAA M//  :  ESCESCOOAA M// Description: Selftest module for Ethernet Phys.  :  ESCESCOOAA M// Project: NetFPGA  :  ESCESCOOAA M// Module: phy_test_pktgen.v  :  ESCESCOOAA M//  :  ESCESCOOAA M// $Id: phy_test_pktgen.v 1794 2007-05-21 01:38:29Z grg $  :  ESCESCOOAA M// vim:set shiftwidth=3 softtabstop=3 expandtab:  :  ESCESCOOAA M///////////////////////////////////////////////////////////////////////////////  :  ESCESCOOAA  :  ESCESCOOAA  :  ESCESCOOAA  :  ESCESCOOAA  :  ESCESCOOAA  :  ESCESCOOAA  :  ESCESCOOAA  :  ESCESCOOAA  :  ESCESCOOAA  :  ESCESCOOAA  :  ESCESCOOAA  :  ESCESCOOAA  :  ESCESCOOAA  :  ESCESCOOAA  :  ESCESCOOAA  :  ESCESCOOBB  ); :  ESCESCOOBB  :  ESCESCOOBB  // Identify different patters :  ESCESCOOBB  localparam ALL_0_PATTERN = 5'b00001; :  ESCESCOOBB  localparam ALL_1_PATTERN = 5'b00010; :  ESCESCOOBB  localparam ALT_01_PATTERN = 5'b00100; :  ESCESCOOBB  localparam ALT_10_PATTERN = 5'b01000; :  ESCESCOOBB  localparam RANDOM_PATTERN = 5'b10000; :  ESCESCOOBB  :  ESCESCOOBB  // Count when the LFSR should be enabled :  ESCESCOOBB  localparam START_LFSR = 'd5; :  ESCESCOOBB  :  ESCESCOOBB  // Word locations of various packet components :  ESCESCOOBB  localparam DA_HI = 'd0; :  ESCESCOOBB  localparam DA_LO_SA_HI = 'd1; :  ESCESCOOBB  localparam SA_LO = 'd2; :  ESCESCOOBB  localparam SIZE_PATTERN = 'd3; :  ESCESCOOBB  localparam SEQUENCE_NO = 'd4; :  ESCESCOOBB  :  ESCESCOOBB  // Packet length related variables :  ESCESCOOBB  reg [8:0] num_words; :  ESCESCOOBB  reg [3:0] final_ctrl; :  ESCESCOOBB  :  ESCESCOOBB  reg [8:0] count; :  ESCESCOOBB  :  ESCESCOOBB  wire [31:0] rand_data; :  ESCESCOOBB  reg [31:0] header_nxt; :  ESCESCOOBB  reg [31:0] payload; :  ESCESCOOBB  reg [31:0] header; :  ESCESCOOBB  :  ESCESCOOBB  reg done_nxt; :  ESCESCOOBB  wire last_word; :  ESCESCOOBB  :  ESCESCOOBB  reg enable_lfsr; :  ESCESCOOBB  :  ESCESCOOBB  reg sel_payload; :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  // ================================= :  ESCESCOOBB  // Main state machine responsible for packet transmission :  ESCESCOOBB  // Tracks the current word and places data on the output signals :  ESCESCOOBB  :  ESCESCOOBB  // Generate the last word signal :  ESCESCOOBB  assign last_word = count == num_words - 1; :  ESCESCOOBB  :  ESCESCOOBB  always @(posedge clk) :  ESCESCOOBB  begin :  ESCESCOOBB  // Track the count and calculate the data to send :  ESCESCOOBB  if (reset) begin :  ESCESCOOBB  count <= 'h0; :  ESCESCOOBB  enable_lfsr <= 1'b0; :  ESCESCOOBB  final_ctrl <= 4'b0000; :  ESCESCOOBB  num_words <= {9{1'b1}}; :  ESCESCOOBB  ctrl <= 'h0; :  ESCESCOOBB  done <= 1'b0; :  ESCESCOOBB  busy <= 1'b0; :  ESCESCOOBB  sel_payload <= 1'b0; :  ESCESCOOBB  header <= 'h0; :  ESCESCOOBB  end :  ESCESCOOBB  else if (rd_en) begin :  ESCESCOOBB  if (last_word) begin :  ESCESCOOBB  // If we are on the last word we should reset the :  ESCESCOOBB  // counter and move to the next pattern :  ESCESCOOBB  // :  ESCESCOOBB  // Don't reset the LFSR here as the output may not :  ESCESCOOBB  // have been processed yet :  ESCESCOOBB  count <= 'h0; :  ESCESCOOBB  final_ctrl <= 4'b0000; :  ESCESCOOBB  num_words <= {9{1'b1}}; :  ESCESCOOBB  ctrl <= final_ctrl; :  ESCESCOOBB  done <= 1'b1; :  ESCESCOOBB  sel_payload <= 1'b1; :  ESCESCOOBB  header <= header_nxt; :  ESCESCOOBB  end :  ESCESCOOBB  else begin :  ESCESCOOBB  // Record the size and pattern if we're :  ESCESCOOBB  // on the appropriate word :  ESCESCOOBB  if (count == SIZE_PATTERN) begin :  ESCESCOOBB  // Work out how many words we expect to send :  ESCESCOOBB  num_words <= pkt_size[10:2] + (|pkt_size[1:0]); :  ESCESCOOBB  :  ESCESCOOBB  // Calculate the control bits for the final word :  ESCESCOOBB  case (pkt_size[1:0]) :  ESCESCOOBB  2'd0 : final_ctrl <= 4'b0001; :  ESCESCOOBB  2'd1 : final_ctrl <= 4'b1000; :  ESCESCOOBB  2'd2 : final_ctrl <= 4'b0100; :  ESCESCOOBB  2'd3 : final_ctrl <= 4'b0010; :  ESCESCOOBB  endcase :  ESCESCOOBB  end :  ESCESCOOBB  :  ESCESCOOBB  // Enable the LFSR if appropriate :  ESCESCOOBB  if (count == START_LFSR) :  ESCESCOOBB  enable_lfsr <= 1'b1; :  ESCESCOOBB  else if (count == 'h0) :  ESCESCOOBB  enable_lfsr <= 1'b0; :  ESCESCOOBB  :  ESCESCOOBB  // If we are not on the last word then we should increment the :  ESCESCOOBB  // counter but don't touch the pattern :  ESCESCOOBB  count <= count + 'h1; :  ESCESCOOBB  header <= header_nxt; :  ESCESCOOBB  ctrl <= 'h0; :  ESCESCOOBB  done <= 1'b0; :  ESCESCOOBB  if (count == 'h0) :  ESCESCOOBB  sel_payload <= 1'b0; :  ESCESCOOBB  else if (count == SEQUENCE_NO) :  ESCESCOOBB  sel_payload <= 1'b1; :  ESCESCOOBB  end :  ESCESCOOBB  busy <= 1'b1; :  ESCESCOOBB  end :  ESCESCOOBB  else if (count == 'h0) :  ESCESCOOBB  busy <= 1'b0; :  ESCESCOOBB  end :  ESCESCOOBB  :  ESCESCOOBB  assign data = sel_payload ? payload : header; :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  // ================================= :  ESCESCOOBB  // Muxes to work out what data to transmit :  ESCESCOOBB  :  ESCESCOOBB  always @* :  ESCESCOOBB  begin :  ESCESCOOBB  case (count) :  ESCESCOOBB  //DA_HI : header_nxt = 32'h 00_ca_fe_00; :  ESCESCOOBB  DA_LO_SA_HI : header_nxt = {8'h 01, 5'd0, port, 16'h 00_ca}; :  ESCESCOOBB  SA_LO : header_nxt = {24'h fe_00_00, 5'd0, port}; :  ESCESCOOBB  SIZE_PATTERN: header_nxt = {4'hf, 1'b0, pkt_size, 8'd0, {(8 - NUM_PATTERNS){1'b0}}, pattern}; :  ESCESCOOBB  default : header_nxt = 32'h 00_ca_fe_00; :  ESCESCOOBB  endcase :  ESCESCOOBB  end :  ESCESCOOBB  :  ESCESCOOBB  always @* :  ESCESCOOBB  begin :  ESCESCOOBB  case (pattern) :  ESCESCOOBB  ALL_0_PATTERN : payload = 32'h 00000000; :  ESCESCOOBB  ALL_1_PATTERN : payload = 32'h ffffffff; :  ESCESCOOBB  ALT_01_PATTERN : payload = 32'h 55555555; :  ESCESCOOBB  ALT_10_PATTERN : payload = 32'h aaaaaaaa; :  ESCESCOOBB  default : payload = rand_data; :  ESCESCOOBB  endcase :  ESCESCOOBB  end :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  // ================================= :  ESCESCOOBB  // LFSR to generate random patterns :  ESCESCOOBB  // :  ESCESCOOBB  // The LFSR should only progress when we are generating a random pattern at :  ESCESCOOBB  // only when we are in the payload section. :  ESCESCOOBB  // :  ESCESCOOBB  // The first word should actually be repeated twice in the payload to allow :  ESCESCOOBB  // the receiver to start an identical LFSR :  ESCESCOOBB  lfsr32 patgen ( :  ESCESCOOBB  .val (rand_data), :  ESCESCOOBB  .rd (pattern == RANDOM_PATTERN && rd_en && enable_lfsr), :  ESCESCOOBB  .seed (seq_no), :  ESCESCOOBB  .reset (reset || !enable_lfsr), :  ESCESCOOBB  .clk (clk) :  ESCESCOOBB  ); :  ESCESCOOBB  :  ESCESCOOAA M  :  ESCESCOOAA M  :  ESCESCOOAA M  :  ESCESCOOAA M assign data = sel_payload ? payload : header;  :  ESCESCOOAA M  :  ESCESCOOAA M end  :  ESCESCOOAA M busy <= 1'b0;  :  ESCESCOOAA M else if (count == 'h0)  :  ESCESCOOAA M end  :  ESCESCOOAA M busy <= 1'b1;  :  ESCESCOOAA M end  :  ESCESCOOAA M sel_payload <= 1'b1;  :  ESCESCOOAA M else if (count == SEQUENCE_NO)  :  ESCESCOOAA M sel_payload <= 1'b0;  :  ESCESCOOAA M if (count == 'h0)  :  ESCESCOOAA M done <= 1'b0;  :  ESCESCOOAA M ctrl <= 'h0;  :  ESCESCOOAA M header <= header_nxt;  :  ESCESCOOAA M count <= count + 'h1;  :  ESCESCOOAA M // counter but don't touch the pattern  :  ESCESCOOAA M // If we are not on the last word then we should increment the  :  ESCESCOOAA M  :  ESCESCOOAA M enable_lfsr <= 1'b0;  :  ESCESCOOAA M else if (count == 'h0)  :  ESCESCOOAA M enable_lfsr <= 1'b1;  :  ESCESCOOAA M if (count == START_LFSR)  :  ESCESCOOAA M // Enable the LFSR if appropriate  :  ESCESCOOAA M  :  ESCESCOOAA M end  :  ESCESCOOAA M endcase  :  ESCESCOOAA M 2'd3 : final_ctrl <= 4'b0010;  :  ESCESCOOAA M 2'd2 : final_ctrl <= 4'b0100;  :  ESCESCOOAA M 2'd1 : final_ctrl <= 4'b1000;  :  ESCESCOOAA M 2'd0 : final_ctrl <= 4'b0001;  :  ESCESCOOAA M case (pkt_size[1:0])  :  ESCESCOOAA M // Calculate the control bits for the final word  :  ESCESCOOAA M  :  ESCESCOOAA M num_words <= pkt_size[10:2] + (|pkt_size[1:0]);  :  ESCESCOOAA M // Work out how many words we expect to send  :  ESCESCOOAA M if (count == SIZE_PATTERN) begin  :  ESCESCOOAA M // on the appropriate word  :  ESCESCOOAA M // Record the size and pattern if we're  :  ESCESCOOAA M else begin  :  ESCESCOOAA M end  :  ESCESCOOAA M header <= header_nxt;  :  ESCESCOOAA M sel_payload <= 1'b1;  :  ESCESCOOAA M done <= 1'b1;  :  ESCESCOOAA M ctrl <= final_ctrl;  :  ESCESCOOAA M num_words <= {9{1'b1}};  :  ESCESCOOAA M final_ctrl <= 4'b0000;  :  ESCESCOOAA M count <= 'h0;  :  ESCESCOOAA M // have been processed yet  :  ESCESCOOAA M // Don't reset the LFSR here as the output may not  :  ESCESCOOAA M //  :  ESCESCOOAA M // counter and move to the next pattern  :  ESCESCOOAA M // If we are on the last word we should reset the  :  ESCESCOOAA M if (last_word) begin  :  ESCESCOOAA M else if (rd_en) begin  :  ESCESCOOAA M end  :  ESCESCOOAA M header <= 'h0;  :  ESCESCOOAA M sel_payload <= 1'b0;  :  ESCESCOOAA M busy <= 1'b0;  :  ESCESCOOAA M done <= 1'b0;  :  ESCESCOOAA M ctrl <= 'h0;  :  ESCESCOOAA M num_words <= {9{1'b1}};  :  ESCESCOOAA M final_ctrl <= 4'b0000;  :  ESCESCOOAA M enable_lfsr <= 1'b0;  :  ESCESCOOAA M count <= 'h0;  :  ESCESCOOAA M if (reset) begin  :  ESCESCOOAA M // Track the count and calculate the data to send  :  ESCESCOOAA M begin  :  ESCESCOOAA M always @(posedge clk)  :  ESCESCOOAA M  :  ESCESCOOAA M assign last_word = count == num_words - 1;  :  ESCESCOOAA M // Generate the last word signal  :  ESCESCOOAA M  :  ESCESCOOAA M // Tracks the current word and places data on the output signals  :  ESCESCOOAA M // Main state machine responsible for packet transmission  :  ESCESCOOAA M // =================================  :  ESCESCOOAA M  :  ESCESCOOAA M  :  ESCESCOOAA M  :  ESCESCOOAA M reg sel_payload;  :  ESCESCOOAA M  :  ESCESCOOAA M reg enable_lfsr;  :  ESCESCOOAA M  :  ESCESCOOAA M wire last_word;  :  ESCESCOOAA M reg done_nxt;  :  ESCESCOOAA M  :  ESCESCOOAA M reg [31:0] header;  :  ESCESCOOAA M reg [31:0] payload;  :  ESCESCOOAA M reg [31:0] header_nxt;  :  ESCESCOOAA M wire [31:0] rand_data;  :  ESCESCOOAA M  :  ESCESCOOAA M reg [8:0] count;  :  ESCESCOOAA M  :  ESCESCOOAA M reg [3:0] final_ctrl;  :  ESCESCOOAA M reg [8:0] num_words;  :  ESCESCOOAA M // Packet length related variables  :  ESCESCOOAA M  :  ESCESCOOAA M localparam SEQUENCE_NO = 'd4;  :  ESCESCOOAA M localparam SIZE_PATTERN = 'd3;  :  ESCESCOOAA M localparam SA_LO = 'd2;  :  ESCESCOOAA M localparam DA_LO_SA_HI = 'd1;  :  ESCESCOOAA M localparam DA_HI = 'd0;  :  ESCESCOOAA M // Word locations of various packet components  :  ESCESCOOAA M  :  ESCESCOOAA M localparam START_LFSR = 'd5;  :  ESCESCOOAA M // Count when the LFSR should be enabled  :  ESCESCOOAA M  :  ESCESCOOAA M localparam RANDOM_PATTERN = 5'b10000;  :  ESCESCOOAA M localparam ALT_10_PATTERN = 5'b01000;  :  ESCESCOOAA M localparam ALT_01_PATTERN = 5'b00100;  :  ESCESCOOAA M localparam ALL_1_PATTERN = 5'b00010;  :  ESCESCOOAA M localparam ALL_0_PATTERN = 5'b00001;  :  ESCESCOOAA M // Identify different patters  :  ESCESCOOAA M  :  ESCESCOOAA M );  :  ESCESCOOAA M input clk  :  ESCESCOOAA M input reset,  :  ESCESCOOAA M //--- misc  :  ESCESCOOAA M  :  ESCESCOOAA M output reg done, // Indicates the last word of the packet is being output  :  ESCESCOOAA M output reg busy, // Currently transmitting packets  :  ESCESCOOAA M  :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  // ================================= :  ESCESCOOBB  // Main state machine responsible for packet transmission :  ESCESCOOBB  // Tracks the current word and places data on the output signals :  ESCESCOOBB  :  ESCESCOOBB  // Generate the last word signal :  ESCESCOOBB  assign last_word = count == num_words - 1; :  ESCESCOOBB  :  ESCESCOOBB  always @(posedge clk) :  ESCESCOOBB  begin :  ESCESCOOBB  // Track the count and calculate the data to send :  ESCESCOOBB  if (reset) begin :  ESCESCOOBB  count <= 'h0; :  ESCESCOOBB  enable_lfsr <= 1'b0; :  ESCESCOOBB  final_ctrl <= 4'b0000; :  ESCESCOOBB  num_words <= {9{1'b1}}; :  ESCESCOOBB  ctrl <= 'h0; :  ESCESCOOBB  done <= 1'b0; :  ESCESCOOBB  busy <= 1'b0; :  ESCESCOOBB  sel_payload <= 1'b0; :  ESCESCOOBB  header <= 'h0; :  ESCESCOOBB  end :  ESCESCOOBB  else if (rd_en) begin :  ESCESCOOBB  if (last_word) begin :  ESCESCOOBB  // If we are on the last word we should reset the :  ESCESCOOBB  // counter and move to the next pattern :  ESCESCOOBB  // :  ESCESCOOAA M reg [3:0] final_ctrl;  :  ESCESCOOAA M reg [8:0] num_words;  :  ESCESCOOAA M // Packet length related variables  :  ESCESCOOAA M  :  ESCESCOOAA M localparam SEQUENCE_NO = 'd4;  :  ESCESCOOAA M localparam SIZE_PATTERN = 'd3;  :  ESCESCOOAA M localparam SA_LO = 'd2;  :  ESCESCOOAA M localparam DA_LO_SA_HI = 'd1;  :  ESCESCOOAA M localparam DA_HI = 'd0;  :  ESCESCOOAA M // Word locations of various packet components  :  ESCESCOOAA M  :  ESCESCOOAA M localparam START_LFSR = 'd5;  :  ESCESCOOAA M // Count when the LFSR should be enabled  :  ESCESCOOAA M  :  ESCESCOOAA M localparam RANDOM_PATTERN = 5'b10000;  :  ESCESCOOAA M localparam ALT_10_PATTERN = 5'b01000;  :  ESCESCOOAA M localparam ALT_01_PATTERN = 5'b00100;  :  ESCESCOOAA M localparam ALL_1_PATTERN = 5'b00010;  :  ESCESCOOAA M localparam ALL_0_PATTERN = 5'b00001;  :  ESCESCOOAA M // Identify different patters  :  ESCESCOOAA M  :  ESCESCOOAA M );  :  ESCESCOOAA M input clk  :  ESCESCOOAA M input reset,  :  ESCESCOOAA M //--- misc  :  ESCESCOOAA M  :  ESCESCOOAA M output reg done, // Indicates the last word of the packet is being output  :  ESCESCOOAA M output reg busy, // Currently transmitting packets  :  ESCESCOOAA M  :  ESCESCOOAA M input [SEQ_NO_WIDTH - 1:0] seq_no, // Initial sequence number  :  ESCESCOOAA M input [10:0] pkt_size, // Packet size  :  ESCESCOOAA M input [NUM_PATTERNS - 1:0] pattern, // Pattern enable  :  ESCESCOOAA M input [2:0] port, // Source port number  :  ESCESCOOAA M  :  ESCESCOOAA M input rd_en, // Output the next word  :  ESCESCOOAA M output reg [3:0] ctrl,  :  ESCESCOOAA M output [31:0] data,  :  ESCESCOOAA M (  :  ESCESCOOAA M )  :  ESCESCOOAA M SEQ_NO_WIDTH = 32  :  ESCESCOOAA M NUM_PATTERNS = 5,  :  ESCESCOOAA M CPCI_NF2_DATA_WIDTH = 32,  :  ESCESCOOAA Mmodule phy_test_pktgen #(parameter  :  ESCESCOOAA M  :  ESCESCOOAA M///////////////////////////////////////////////////////////////////////////////  :  ESCESCOOAA M//  :  ESCESCOOAA M// Note: data is muxed -- not the direct output for a flop  :  ESCESCOOAA M//  :  ESCESCOOBB  localparam SEQUENCE_NO = 'd4; :  ESCESCOOBB  :  ESCESCOOBB  // Packet length related variables :  ESCESCOOBB  reg [8:0] num_words; :  ESCESCOOBB  reg [3:0] final_ctrl; :  ESCESCOOBB  :  ESCESCOOBB  reg [8:0] count; :  ESCESCOOBB  :  ESCESCOOBB  wire [31:0] rand_data; :  ESCESCOOBB  reg [31:0] header_nxt; :  ESCESCOOBB  reg [31:0] payload; :  ESCESCOOBB  reg [31:0] header; :  ESCESCOOBB  :  ESCESCOOBB  reg done_nxt; :  ESCESCOOBB  wire last_word; :  ESCESCOOBB  :  ESCESCOOBB  reg enable_lfsr; :  ESCESCOOBB  :  ESCESCOOBB  reg sel_payload; :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  // ================================= :  ESCESCOOBB  // Main state machine responsible for packet transmission :  ESCESCOOBB  // Tracks the current word and places data on the output signals :  ESCESCOOBB  :  ESCESCOOBB  // Generate the last word signal :  ESCESCOOBB  assign last_word = count == num_words - 1; :  ESCESCOOBB  :  ESCESCOOBB  always @(posedge clk) :  ESCESCOOBB  begin :  ESCESCOOBB  // Track the count and calculate the data to send :  ESCESCOOBB  if (reset) begin :  ESCESCOOBB  count <= 'h0; :  ESCESCOOBB  enable_lfsr <= 1'b0; :  ESCESCOOBB  final_ctrl <= 4'b0000; :  ESCESCOOBB  num_words <= {9{1'b1}}; :  ESCESCOOBB  ctrl <= 'h0; :  ESCESCOOBB  done <= 1'b0; :  ESCESCOOBB  busy <= 1'b0; :  ESCESCOOBB  sel_payload <= 1'b0; :  ESCESCOOBB  header <= 'h0; :  ESCESCOOBB  end :  ESCESCOOBB  else if (rd_en) begin :  ESCESCOOBB  if (last_word) begin :  ESCESCOOBB  // If we are on the last word we should reset the :  ESCESCOOBB  // counter and move to the next pattern :  ESCESCOOBB  // :  ESCESCOOBB  // Don't reset the LFSR here as the output may not :  ESCESCOOBB  // have been processed yet :  ESCESCOOBB  count <= 'h0; :  ESCESCOOBB  final_ctrl <= 4'b0000; :  ESCESCOOBB  num_words <= {9{1'b1}}; :  ESCESCOOBB  ctrl <= final_ctrl; :  ESCESCOOBB  done <= 1'b1; :  ESCESCOOBB  sel_payload <= 1'b1; :  ESCESCOOBB  header <= header_nxt; :  ESCESCOOBB  end :  ESCESCOOBB  else begin :  ESCESCOOBB  // Record the size and pattern if we're :  ESCESCOOBB  // on the appropriate word :  ESCESCOOBB  if (count == SIZE_PATTERN) begin :  ESCESCOOBB  // Work out how many words we expect to send :  ESCESCOOBB  num_words <= pkt_size[10:2] + (|pkt_size[1:0]); :  ESCESCOOBB  :  ESCESCOOBB  // Calculate the control bits for the final word :  ESCESCOOBB  case (pkt_size[1:0]) :  ESCESCOOBB  2'd0 : final_ctrl <= 4'b0001; :  ESCESCOOBB  2'd1 : final_ctrl <= 4'b1000; :  ESCESCOOBB  2'd2 : final_ctrl <= 4'b0100; :  ESCESCOOBB  2'd3 : final_ctrl <= 4'b0010; :  ESCESCOOBB  endcase :  ESCESCOOBB  end :  ESCESCOOBB  :  ESCESCOOBB  // Enable the LFSR if appropriate :  ESCESCOOBB  if (count == START_LFSR) :  ESCESCOOBB  enable_lfsr <= 1'b1; :  ESCESCOOBB  else if (count == 'h0) :  ESCESCOOBB  enable_lfsr <= 1'b0; :  ESCESCOOBB  :  ESCESCOOBB  // If we are not on the last word then we should increment the :  ESCESCOOBB  // counter but don't touch the pattern :  ESCESCOOBB  count <= count + 'h1; :  ESCESCOOBB  header <= header_nxt; :  ESCESCOOBB  ctrl <= 'h0; :  ESCESCOOBB  done <= 1'b0; :  ESCESCOOBB  if (count == 'h0) :  ESCESCOOBB  sel_payload <= 1'b0; :  ESCESCOOBB  else if (count == SEQUENCE_NO) :  ESCESCOOBB  sel_payload <= 1'b1; :  ESCESCOOBB  end :  ESCESCOOBB  busy <= 1'b1; :  ESCESCOOBB  end :  ESCESCOOBB  else if (count == 'h0) :  ESCESCOOBB  busy <= 1'b0; :  ESCESCOOBB  end :  ESCESCOOBB  :  ESCESCOOBB  assign data = sel_payload ? payload : header; :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  // ================================= :  ESCESCOOBB  // Muxes to work out what data to transmit :  ESCESCOOBB  :  ESCESCOOBB  always @* :  ESCESCOOBB  begin :  ESCESCOOBB  case (count) :  ESCESCOOBB  //DA_HI : header_nxt = 32'h 00_ca_fe_00; :  ESCESCOOBB  DA_LO_SA_HI : header_nxt = {8'h 01, 5'd0, port, 16'h 00_ca}; :  ESCESCOOBB  SA_LO : header_nxt = {24'h fe_00_00, 5'd0, port}; :  ESCESCOOBB  SIZE_PATTERN: header_nxt = {4'hf, 1'b0, pkt_size, 8'd0, {(8 - NUM_PATTERNS){1'b0}}, pattern}; :  ESCESCOOBB  default : header_nxt = 32'h 00_ca_fe_00; :  ESCESCOOBB  endcase :  ESCESCOOBB  end :  ESCESCOOBB  :  ESCESCOOBB  always @* :  ESCESCOOBB  begin :  ESCESCOOBB  case (pattern) :  ESCESCOOBB  ALL_0_PATTERN : payload = 32'h 00000000; :  ESCESCOOBB  ALL_1_PATTERN : payload = 32'h ffffffff; :  ESCESCOOBB  ALT_01_PATTERN : payload = 32'h 55555555; :  ESCESCOOBB  ALT_10_PATTERN : payload = 32'h aaaaaaaa; :  ESCESCOOBB  default : payload = rand_data; :  ESCESCOOBB  endcase :  ESCESCOOBB  end :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  // ================================= :  ESCESCOOBB  // LFSR to generate random patterns :  ESCESCOOBB  // :  ESCESCOOBB  // The LFSR should only progress when we are generating a random pattern at :  ESCESCOOBB  // only when we are in the payload section. :  ESCESCOOBB  // :  ESCESCOOBB  // The first word should actually be repeated twice in the payload to allow :  ESCESCOOBB  // the receiver to start an identical LFSR :  ESCESCOOBB  lfsr32 patgen ( :  ESCESCOOBB  .val (rand_data), :  ESCESCOOBB  .rd (pattern == RANDOM_PATTERN && rd_en && enable_lfsr), :  ESCESCOOBB  .seed (seq_no), :  ESCESCOOBB  .reset (reset || !enable_lfsr), :  ESCESCOOBB  .clk (clk) :  ESCESCOOBB  ); :  ESCESCOOBB  :  ESCESCOOBB endmodule // phy_test_pktgen (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOAA M // =================================  :  ESCESCOOBB endmodule // phy_test_pktgen (END)   ESCESCOOAA M // =================================  :  ESCESCOOAA M  :  ESCESCOOAA M  :  ESCESCOOAA M  :  ESCESCOOAA M assign data = sel_payload ? payload : header;  :  ESCESCOOAA M  :  ESCESCOOAA M end  :  ESCESCOOAA M busy <= 1'b0;  :  ESCESCOOAA M else if (count == 'h0)  :  ESCESCOOAA M end  :  ESCESCOOAA M busy <= 1'b1;  :  ESCESCOOAA M end  :  ESCESCOOAA M sel_payload <= 1'b1;  :  ESCESCOOAA M else if (count == SEQUENCE_NO)  :  ESCESCOOAA M sel_payload <= 1'b0;  :  ESCESCOOAA M if (count == 'h0)  :  ESCESCOOAA M done <= 1'b0;  :  ESCESCOOAA M ctrl <= 'h0;  :  ESCESCOOAA M header <= header_nxt;  :  ESCESCOOAA M count <= count + 'h1;  :  ESCESCOOAA M // counter but don't touch the pattern  :  ESCESCOOAA M // If we are not on the last word then we should increment the  :  ESCESCOOAA M  :  ESCESCOOAA M enable_lfsr <= 1'b0;  :  ESCESCOOAA M else if (count == 'h0)  :  ESCESCOOAA M enable_lfsr <= 1'b1;  :  ESCESCOOAA M if (count == START_LFSR)  :  ESCESCOOAA M // Enable the LFSR if appropriate  :  ESCESCOOAA M  :  ESCESCOOAA M end  :  ESCESCOOAA M endcase  :  ESCESCOOAA M 2'd3 : final_ctrl <= 4'b0010;  :  ESCESCOOAA M 2'd2 : final_ctrl <= 4'b0100;  :  ESCESCOOAA M 2'd1 : final_ctrl <= 4'b1000;  :  ESCESCOOAA M 2'd0 : final_ctrl <= 4'b0001;  :  ESCESCOOAA M case (pkt_size[1:0])  :  ESCESCOOAA M // Calculate the control bits for the final word  :  ESCESCOOAA M  :  ESCESCOOAA M num_words <= pkt_size[10:2] + (|pkt_size[1:0]);  :  ESCESCOOAA M // Work out how many words we expect to send  :  ESCESCOOAA M if (count == SIZE_PATTERN) begin  :  ESCESCOOAA M // on the appropriate word  :  ESCESCOOAA M // Record the size and pattern if we're  :  ESCESCOOAA M else begin  :  ESCESCOOAA M end  :  ESCESCOOAA M header <= header_nxt;  :  ESCESCOOAA M sel_payload <= 1'b1;  :  ESCESCOOAA M done <= 1'b1;  :  ESCESCOOAA M ctrl <= final_ctrl;  :  ESCESCOOAA M num_words <= {9{1'b1}};  :  ESCESCOOAA M final_ctrl <= 4'b0000;  :  ESCESCOOAA M count <= 'h0;  :  ESCESCOOAA M // have been processed yet  :  ESCESCOOAA M // Don't reset the LFSR here as the output may not  :  ESCESCOOAA M //  :  ESCESCOOAA M // counter and move to the next pattern  :  ESCESCOOAA M // If we are on the last word we should reset the  :  ESCESCOOAA M if (last_word) begin  :  ESCESCOOAA M else if (rd_en) begin  :  ESCESCOOAA M end  :  ESCESCOOAA M header <= 'h0;  :  ESCESCOOAA M sel_payload <= 1'b0;  :  ESCESCOOAA M busy <= 1'b0;  :  ESCESCOOAA M done <= 1'b0;  :  ESCESCOOAA M ctrl <= 'h0;  :  ESCESCOOAA M num_words <= {9{1'b1}};  :  ESCESCOOAA M final_ctrl <= 4'b0000;  :  ESCESCOOAA M enable_lfsr <= 1'b0;  :  ESCESCOOAA M count <= 'h0;  :  ESCESCOOAA M if (reset) begin  :  ESCESCOOAA M // Track the count and calculate the data to send  :  ESCESCOOAA M begin  :  ESCESCOOAA M always @(posedge clk)  :  ESCESCOOAA M  :  ESCESCOOAA M assign last_word = count == num_words - 1;  :  ESCESCOOAA M // Generate the last word signal  :  ESCESCOOAA M  :  ESCESCOOAA M // Tracks the current word and places data on the output signals  :  ESCESCOOAA M // Main state machine responsible for packet transmission  :  ESCESCOOAA M // =================================  :  ESCESCOOAA M  :  ESCESCOOAA M  :  ESCESCOOAA M  :  ESCESCOOAA M reg sel_payload;  :  ESCESCOOAA M  :  ESCESCOOAA M reg enable_lfsr;  :  ESCESCOOAA M  :  ESCESCOOAA M wire last_word;  :  ESCESCOOAA M reg done_nxt;  :  ESCESCOOAA M  :  ESCESCOOAA M reg [31:0] header;  :  ESCESCOOAA M reg [31:0] payload;  :  ESCESCOOAA M reg [31:0] header_nxt;  :  ESCESCOOAA M wire [31:0] rand_data;  :  ESCESCOOAA M  :  ESCESCOOAA M reg [8:0] count;  :  ESCESCOOAA M  :  ESCESCOOAA M reg [3:0] final_ctrl;  :  ESCESCOOAA M reg [8:0] num_words;  :  ESCESCOOAA M // Packet length related variables  :  ESCESCOOAA M  :  ESCESCOOAA M localparam SEQUENCE_NO = 'd4;  :  ESCESCOOAA M localparam SIZE_PATTERN = 'd3;  :  ESCESCOOAA M localparam SA_LO = 'd2;  :  ESCESCOOAA M localparam DA_LO_SA_HI = 'd1;  :  ESCESCOOAA M localparam DA_HI = 'd0;  :  ESCESCOOAA M // Word locations of various packet components  :  ESCESCOOAA M  :  ESCESCOOAA M localparam START_LFSR = 'd5;  :  ESCESCOOAA M // Count when the LFSR should be enabled  :  ESCESCOOAA M  :  ESCESCOOAA M localparam RANDOM_PATTERN = 5'b10000;  :  ESCESCOOAA M localparam ALT_10_PATTERN = 5'b01000;  :  ESCESCOOAA M localparam ALT_01_PATTERN = 5'b00100;  :  ESCESCOOAA M localparam ALL_1_PATTERN = 5'b00010;  :  ESCESCOOAA M localparam ALL_0_PATTERN = 5'b00001;  :  ESCESCOOAA M // Identify different patters  :  ESCESCOOAA M  :  ESCESCOOAA M );  :  ESCESCOOAA M input clk  :  ESCESCOOAA M input reset,  :  ESCESCOOAA M //--- misc  :  ESCESCOOAA M  :  ESCESCOOAA M output reg done, // Indicates the last word of the packet is being output  :  ESCESCOOAA M output reg busy, // Currently transmitting packets  :  ESCESCOOAA M  :  ESCESCOOAA M input [SEQ_NO_WIDTH - 1:0] seq_no, // Initial sequence number  :  ESCESCOOAA M input [10:0] pkt_size, // Packet size  :  ESCESCOOAA M input [NUM_PATTERNS - 1:0] pattern, // Pattern enable  :  ESCESCOOAA M input [2:0] port, // Source port number  :  ESCESCOOAA M  :  ESCESCOOAA M input rd_en, // Output the next word  :  ESCESCOOAA M output reg [3:0] ctrl,  :  ESCESCOOAA M output [31:0] data,  :  ESCESCOOAA M (  :  ESCESCOOAA M )  :  ESCESCOOAA M SEQ_NO_WIDTH = 32  :  ESCESCOOAA M NUM_PATTERNS = 5,  :  ESCESCOOAA M CPCI_NF2_DATA_WIDTH = 32,  :  ESCESCOOAA Mmodule phy_test_pktgen #(parameter  :  ESCESCOOAA M  :  ESCESCOOAA M///////////////////////////////////////////////////////////////////////////////  :  ESCESCOOAA M//  :  ESCESCOOAA M// Note: data is muxed -- not the direct output for a flop  :  ESCESCOOAA M//  :  ESCESCOOAA M// Pattern  :  ESCESCOOAA M// seq_no (or 0)  :  ESCESCOOAA M// Data: 8'b0, pattern (8 bits)  :  ESCESCOOAA M// Length: Length  :  ESCESCOOAA M// SA: 00:ca:fe:00:00:Port  :  ESCESCOOAA M// DA: 00:ca:fe:00:01:Port  :  ESCESCOOAA M//  :  ESCESCOOAA M// only. The packet format is as follows:  :  ESCESCOOAA M// This particular module is responsible for generating packets  :  ESCESCOOAA M//  :  ESCESCOOAA M// Description: Selftest module for Ethernet Phys.  :  ESCESCOOAA M// Project: NetFPGA  :  ESCESCOOAA M// Module: phy_test_pktgen.v  :  ESCESCOOAA M//  :  ESCESCOOAA M// $Id: phy_test_pktgen.v 1794 2007-05-21 01:38:29Z grg $  :  ESCESCOOAA M// vim:set shiftwidth=3 softtabstop=3 expandtab:  :  ESCESCOOAA M///////////////////////////////////////////////////////////////////////////////  :  ESCESCOOAA  :  ESCESCOOAA  :  ESCESCOOAA  :  ESCESCOOAA  :  ESCESCOOAA  :  ESCESCOOAA  :  ESCESCOOBB  ); :  ESCESCOOBB  :  ESCESCOOBB  // Identify different patters :  ESCESCOOBB  localparam ALL_0_PATTERN = 5'b00001; :  ESCESCOOAA M//  :  ESCESCOOAA M// $Id: phy_test_pktgen.v 1794 2007-05-21 01:38:29Z grg $  :  ESCESCOOAA M// vim:set shiftwidth=3 softtabstop=3 expandtab:  :  ESCESCOOAA M///////////////////////////////////////////////////////////////////////////////  :  ESCESCOOAA  :  ESCESCOOAA  :  ESCESCOOAA  :  ESCESCOOAA  :  ESCESCOOBB  ); :  ESCESCOOBB  :  ESCESCOOBB  // Identify different patters :  ESCESCOOBB  localparam ALL_0_PATTERN = 5'b00001; :  ESCESCOOBB  localparam ALL_1_PATTERN = 5'b00010; :  ESCESCOOBB  localparam ALT_01_PATTERN = 5'b00100; :  ESCESCOOBB  localparam ALT_10_PATTERN = 5'b01000; :  ESCESCOOBB  localparam RANDOM_PATTERN = 5'b10000; :  ESCESCOOBB  :  ESCESCOOBB  // Count when the LFSR should be enabled :  ESCESCOOBB  localparam START_LFSR = 'd5; :  ESCESCOOBB  :  ESCESCOOBB  // Word locations of various packet components :  ESCESCOOBB  localparam DA_HI = 'd0; :  ESCESCOOBB  localparam DA_LO_SA_HI = 'd1; :  ESCESCOOBB  localparam SA_LO = 'd2; :  ESCESCOOBB  localparam SIZE_PATTERN = 'd3; :  ESCESCOOBB  localparam SEQUENCE_NO = 'd4; :  ESCESCOOBB  :  ESCESCOOBB  // Packet length related variables :  ESCESCOOBB  reg [8:0] num_words; :  ESCESCOOBB  reg [3:0] final_ctrl; :  ESCESCOOBB  :  ESCESCOOBB  reg [8:0] count; :  ESCESCOOBB  :  ESCESCOOBB  wire [31:0] rand_data; :  ESCESCOOBB  reg [31:0] header_nxt; :  ESCESCOOBB  reg [31:0] payload; :  ESCESCOOBB  reg [31:0] header; :  ESCESCOOBB  :  ESCESCOOBB  reg done_nxt; :  ESCESCOOBB  wire last_word; :  ESCESCOOBB  :  ESCESCOOBB  reg enable_lfsr; :  ESCESCOOBB  :  ESCESCOOBB  reg sel_payload; :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  // ================================= :  ESCESCOOBB  // Main state machine responsible for packet transmission :  ESCESCOOBB  // Tracks the current word and places data on the output signals :  ESCESCOOBB  :  ESCESCOOBB  // Generate the last word signal :  ESCESCOOBB  assign last_word = count == num_words - 1; :  ESCESCOOBB  :  ESCESCOOBB  always @(posedge clk) :  ESCESCOOBB  begin :  ESCESCOOBB  // Track the count and calculate the data to send :  ESCESCOOBB  if (reset) begin :  ESCESCOOBB  count <= 'h0; :  ESCESCOOBB  enable_lfsr <= 1'b0; :  ESCESCOOBB  final_ctrl <= 4'b0000; :  ESCESCOOBB  num_words <= {9{1'b1}}; :  ESCESCOOBB  ctrl <= 'h0; :  ESCESCOOBB  done <= 1'b0; :  ESCESCOOBB  busy <= 1'b0; :  ESCESCOOBB  sel_payload <= 1'b0; :  ESCESCOOBB  header <= 'h0; :  ESCESCOOBB  end :  ESCESCOOBB  else if (rd_en) begin :  ESCESCOOBB  if (last_word) begin :  ESCESCOOBB  // If we are on the last word we should reset the :  ESCESCOOBB  // counter and move to the next pattern :  ESCESCOOBB  // :  ESCESCOOBB  // Don't reset the LFSR here as the output may not :  ESCESCOOBB  // have been processed yet :  ESCESCOOBB  count <= 'h0; :  ESCESCOOBB  final_ctrl <= 4'b0000; :  ESCESCOOBB  num_words <= {9{1'b1}}; :  ESCESCOOBB  ctrl <= final_ctrl; :  ESCESCOOBB  done <= 1'b1; :  ESCESCOOBB  sel_payload <= 1'b1; :  ESCESCOOBB  header <= header_nxt; :  ESCESCOOBB  end :  ESCESCOOBB  else begin :  ESCESCOOBB  // Record the size and pattern if we're :  ESCESCOOBB  // on the appropriate word :  ESCESCOOBB  if (count == SIZE_PATTERN) begin :  ESCESCOOBB  // Work out how many words we expect to send :  ESCESCOOBB  num_words <= pkt_size[10:2] + (|pkt_size[1:0]); :  ESCESCOOBB  :  ESCESCOOBB  // Calculate the control bits for the final word :  ESCESCOOBB  case (pkt_size[1:0]) :  ESCESCOOBB  2'd0 : final_ctrl <= 4'b0001; :  ESCESCOOBB  2'd1 : final_ctrl <= 4'b1000; :  ESCESCOOBB  2'd2 : final_ctrl <= 4'b0100; :  ESCESCOOBB  2'd3 : final_ctrl <= 4'b0010; :  ESCESCOOBB  endcase :  ESCESCOOBB  end :  ESCESCOOBB  :  ESCESCOOBB  // Enable the LFSR if appropriate :  ESCESCOOBB  if (count == START_LFSR) :  ESCESCOOBB  enable_lfsr <= 1'b1; :  ESCESCOOBB  else if (count == 'h0) :  ESCESCOOBB  enable_lfsr <= 1'b0; :  ESCESCOOBB  :  ESCESCOOBB  // If we are not on the last word then we should increment the :  ESCESCOOBB  // counter but don't touch the pattern :  ESCESCOOBB  count <= count + 'h1; :  ESCESCOOBB  header <= header_nxt; :  ESCESCOOBB  ctrl <= 'h0; :  ESCESCOOBB  done <= 1'b0; :  ESCESCOOBB  if (count == 'h0) :  ESCESCOOBB  sel_payload <= 1'b0; :  ESCESCOOBB  else if (count == SEQUENCE_NO) :  ESCESCOOBB  sel_payload <= 1'b1; :  ESCESCOOBB  end :  ESCESCOOBB  busy <= 1'b1; :  ESCESCOOBB  end :  ESCESCOOBB  else if (count == 'h0) :  ESCESCOOBB  busy <= 1'b0; :  ESCESCOOBB  end :  ESCESCOOBB  :  ESCESCOOBB  assign data = sel_payload ? payload : header; :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  // ================================= :  ESCESCOOBB  // Muxes to work out what data to transmit :  ESCESCOOBB  :  ESCESCOOBB  always @* :  ESCESCOOBB  begin :  ESCESCOOBB  case (count) :  ESCESCOOBB  //DA_HI : header_nxt = 32'h 00_ca_fe_00; :  ESCESCOOBB  DA_LO_SA_HI : header_nxt = {8'h 01, 5'd0, port, 16'h 00_ca}; :  ESCESCOOBB  SA_LO : header_nxt = {24'h fe_00_00, 5'd0, port}; :  ESCESCOOBB  SIZE_PATTERN: header_nxt = {4'hf, 1'b0, pkt_size, 8'd0, {(8 - NUM_PATTERNS){1'b0}}, pattern}; :  ESCESCOOBB  default : header_nxt = 32'h 00_ca_fe_00; :  ESCESCOOBB  endcase :  ESCESCOOBB  end :  ESCESCOOBB  :  ESCESCOOBB  always @* :  ESCESCOOBB  begin :  ESCESCOOBB  case (pattern) :  ESCESCOOBB  ALL_0_PATTERN : payload = 32'h 00000000; :  ESCESCOOBB  ALL_1_PATTERN : payload = 32'h ffffffff; :  ESCESCOOBB  ALT_01_PATTERN : payload = 32'h 55555555; :  ESCESCOOBB  ALT_10_PATTERN : payload = 32'h aaaaaaaa; :  ESCESCOOBB  default : payload = rand_data; :  ESCESCOOBB  endcase :  ESCESCOOBB  end :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  // ================================= :  ESCESCOOBB  // LFSR to generate random patterns :  ESCESCOOBB  // :  ESCESCOOBB  // The LFSR should only progress when we are generating a random pattern at :  ESCESCOOBB  // only when we are in the payload section. :  ESCESCOOBB  // :  ESCESCOOBB  // The first word should actually be repeated twice in the payload to allow :  ESCESCOOBB  // the receiver to start an identical LFSR :  ESCESCOOBB  lfsr32 patgen ( :  ESCESCOOBB  .val (rand_data), :  ESCESCOOBB  .rd (pattern == RANDOM_PATTERN && rd_en && enable_lfsr), :  ESCESCOOBB  .seed (seq_no), :  ESCESCOOBB  .reset (reset || !enable_lfsr), :  ESCESCOOBB  .clk (clk) :  ESCESCOOBB  ); :  ESCESCOOBB  :  ESCESCOOBB endmodule // phy_test_pktgen (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)   ESCESCOOBB  (END)  [?1l>[?1049l]0;netfpga@node1-1: ~/netfpga/projects/selftest/srcnetfpga@node1-1:~/netfpga/projects/selftest/src$ less phy_test_pktcmp.v [?1049h[?1h= /////////////////////////////////////////////////////////////////////////////// // vim:set shiftwidth=3 softtabstop=3 expandtab: // $Id: phy_test_pktcmp.v 1799 2007-05-22 03:18:34Z grg $ // // Module: phy_test_pktgen.v // Project: NetFPGA // Description: Selftest module for Ethernet Phys. // // This particular module is responsible for comparing packets // that arrive on an interface // // Note: There is one extra word received after the last data word that // indicates success/failure (eg. FCS error) // /////////////////////////////////////////////////////////////////////////////// module phy_test_pktcmp #(parameter CPCI_NF2_DATA_WIDTH = 32, NUM_PATTERNS = 5, SEQ_NO_WIDTH = 32 ) ( //--- sigs to/from nf2_mac_grp for RX Fifos (ingress) input rx_almost_empty, input [35:0] rx_data, output reg rx_rd_en, //--- sigs to/from phy_test to coordinate the tests output [2:0] port, // Source port number output [NUM_PATTERNS - 1:0] pattern, // Pattern number being received input [10:0] pkt_size, // Packet size input [NUM_PATTERNS - 1:0] pat_en, // Pattern enable output reg [SEQ_NO_WIDTH - 1:0] seq_no, // Sequence number of received packet output reg locked, // Is the state machine currently locked output busy, // Currently receiving a packets output reg done, // Pulses when a packet has been recieved output reg bad, // Indicates whether the received packet was good // and expected phy_test_pktcmp.v   ESCESCOOBB  // RX log interface :  ESCESCOOBB  output reg [31:0] log_rx_data, :  ESCESCOOBB  output reg [31:0] log_exp_data, :  ESCESCOOBB  output reg [8:0] log_addr, :  ESCESCOOBB  output reg log_data_wr, :  ESCESCOOBB  output reg log_done, :  ESCESCOOAA M// Project: NetFPGA  :  ESCESCOOAA M// Module: phy_test_pktgen.v  :  ESCESCOOAA M//  :  ESCESCOOBB  output reg [8:0] log_addr, :  ESCESCOOBB  output reg log_data_wr, :  ESCESCOOBB  output reg log_done, :  ESCESCOOBB  output reg log_hold, :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  //--- misc :  ESCESCOOBB  input reset, :  ESCESCOOBB  input clk :  ESCESCOOBB  ); :  ESCESCOOBB  :  ESCESCOOBB  // Lose lock after 125,000 clock ticks (1ms/2ms depending on core clock :  ESCESCOOBB  // freq) :  ESCESCOOBB  localparam LOSE_LOCK_COUNT = 'd125000; :  ESCESCOOBB  :  ESCESCOOBB  // Identify different patters :  ESCESCOOBB  localparam ALL_0_PATTERN = 5'b00001; :  ESCESCOOBB  localparam ALL_1_PATTERN = 5'b00010; :  ESCESCOOBB  localparam ALT_01_PATTERN = 5'b00100; :  ESCESCOOBB  localparam ALT_10_PATTERN = 5'b01000; :  ESCESCOOBB  localparam RANDOM_PATTERN = 5'b10000; :  ESCESCOOBB  :  ESCESCOOBB  // Count when the LFSR should be enabled :  ESCESCOOBB  localparam START_LFSR = 4; :  ESCESCOOBB  :  ESCESCOOBB  // Word locations of various packet components :  ESCESCOOBB  localparam DA_HI = 'd0; :  ESCESCOOBB  localparam DA_LO_SA_HI = 'd1; :  ESCESCOOBB  localparam SA_LO = 'd2; :  ESCESCOOBB  localparam SIZE_PATTERN = 'd3; :  ESCESCOOBB  localparam SEQUENCE_NO = 'd4; :  ESCESCOOBB  localparam EOP = ~{10'd0}; :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  // Counter to identify when to leave the lock state :  ESCESCOOBB  reg [19:0] lock_count; :  ESCESCOOBB  reg [19:0] lock_count_nxt; :  ESCESCOOBB  :  ESCESCOOBB  // Current/next pattern tracking :  ESCESCOOBB  reg [NUM_PATTERNS - 1 : 0] curr_pat; :  ESCESCOOBB  reg [NUM_PATTERNS - 1 : 0] next_pat; :  ESCESCOOBB  :  ESCESCOOBB  // Packet length related variables :  ESCESCOOBB  reg [10:0] size; :  ESCESCOOBB  reg [10:0] size_nxt; :  ESCESCOOBB  :  ESCESCOOBB  reg [9:0] count; :  ESCESCOOBB  reg [9:0] count_d1; :  ESCESCOOBB  reg [9:0] last_pos; :  ESCESCOOBB  :  ESCESCOOBB  reg done_nxt; :  ESCESCOOBB  :  ESCESCOOBB  reg locked_nxt; :  ESCESCOOBB  :  ESCESCOOBB  reg rx_rd_en_d1; :  ESCESCOOBB  reg rx_rd_en_d2; :  ESCESCOOBB  reg bad_nxt; :  ESCESCOOBB  :  ESCESCOOBB  reg [2:0] curr_port; :  ESCESCOOBB  reg [2:0] curr_port_nxt; :  ESCESCOOBB  :  ESCESCOOBB  reg [NUM_PATTERNS - 1:0] curr_pat_nxt; :  ESCESCOOBB  :  ESCESCOOBB  reg [SEQ_NO_WIDTH - 1:0] seq_no_nxt; :  ESCESCOOBB  :  ESCESCOOBB  wire [3:0] ctrl; :  ESCESCOOBB  reg [3:0] ctrl_d1; :  ESCESCOOBB  wire [31:0] data; :  ESCESCOOBB  reg [31:0] data_d1; :  ESCESCOOBB  :  ESCESCOOBB  wire [31:0] gen_data; :  ESCESCOOBB  reg [31:0] gen_data_d1; :  ESCESCOOBB  wire [3:0] gen_ctrl; :  ESCESCOOBB  wire gen_rd_en; :  ESCESCOOBB  :  ESCESCOOBB  reg eop; :  ESCESCOOBB  reg eop_nxt; :  ESCESCOOBB  :  ESCESCOOBB  reg rx_data_good; :  ESCESCOOBB  reg rx_da_sa_good; :  ESCESCOOBB  reg rx_size_pat_good; :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  // Create the ctrl/data signals :  ESCESCOOBB  :  ESCESCOOBB  assign ctrl = {rx_data[35], rx_data[26], rx_data[17], rx_data[8]}; :  ESCESCOOBB  assign data = {rx_data[34:27], rx_data[25:18], rx_data[16:9], rx_data[7:0]}; :  ESCESCOOBB  :  ESCESCOOBB  // Copy the port and pattern to their outputs :  ESCESCOOBB  assign port = curr_port; :  ESCESCOOBB  assign pattern = curr_pat; :  ESCESCOOBB  :  ESCESCOOBB  // Generate the busy signal :  ESCESCOOBB  assign busy = count != 'h0 || !rx_almost_empty; :  ESCESCOOBB  :  ESCESCOOBB  assign gen_rd_en = rx_rd_en; :  ESCESCOOBB  :  ESCESCOOBB  :  ESCESCOOBB  // ================================= :  ESCESCOOBB  // Main state machine :  ESCESCOOBB  :  ESCESCOOBB  always @(posedge clk) :  ESCESCOOBB  begin :  ESCESCOOBB  bad <= bad_nxt; :  ESCESCOOBB  done <= done_nxt; :  ESCESCOOBB  :  ESCESCOOBB  curr_port <= curr_port_nxt; :  ESCESCOOBB  curr_pat <= curr_pat_nxt; :  ESCESCOOBB  seq_no <= seq_no_nxt; :  ESCESCOOBB  size <= size_nxt; :  ESCESCOOBB  eop <= eop_nxt; :  ESCESCOOBB  end :  ESCESCOOBB  :  ESCESCOOBB  // State machine to monitor incoming data :  ESCESCOOBB  always @* :  ESCESCOOBB  begin :  ESCESCOOBB  // Set variables to their default values :  ESCESCOOBB  bad_nxt = bad; :  ESCESCOOBB  done_nxt = 1'b0; :  ESCESCOOBB  :  ESCESCOOBB  curr_port_nxt = curr_port; :  ESCESCOOBB  curr_pat_nxt = curr_pat; :  ESCESCOOBB  seq_no_nxt = seq_no; :  ESCESCOOBB  size_nxt = size; :  ESCESCOOBB  eop_nxt = eop; :  ESCESCOOBB  :  ESCESCOOBB  if (reset) begin :  ESCESCOOBB  bad_nxt = 1'b0; :  ESCESCOOBB  curr_port_nxt = 'h0; :  ESCESCOOBB  curr_pat_nxt = 'h0; :  ESCESCOOBB  seq_no_nxt = 'h0; : [?1l>[?1049l]0;netfpga@node1-1: ~/netfpga/projects/selftest/srcnetfpga@node1-1:~/netfpga/projects/selftest/src$ pwd /home/netfpga/netfpga/projects/selftest/src ]0;netfpga@node1-1: ~/netfpga/projects/selftest/srcnetfpga@node1-1:~/netfpga/projects/selftest/src$ clear ]0;netfpga@node1-1: ~/netfpga/projects/selftest/srcnetfpga@node1-1:~/netfpga/projects/selftest/src$ sudo su - ]0;root@node1-1.sb9.orbit-lab.org: ~root@node1-1:~# exitclearlear~netfpga/netfpga/projects/selftest/sw/selftest -cn Found net device: nf2c0 CPCI Information ---------------- Version: 4 (rev 1) Device (Virtex) Information --------------------------- Project directory: selftest Project name: Selftest Project description: NetFPGA selftest -- exercises all major subsystems of the board Device ID: 5 Version: 1.1.0 Built against CPCI version: 4 (rev 1) [?1049h(B[?7h(B NetFPGA selftest v1.00 alpha (BClock test: pass Reg test: pass MDIO test: pass Phy 1: rev 1 up, 1000Base-TX full Phy 2: rev 1 up, 1000Base-TX full Phy 3: rev 1 up, 1000Base-TX full Phy 4: rev 1 up, 1000Base-TX full PHY test: fail Port 1: link w/ 3 Good: 17261 Bad: 0 Port 2: link w/ 4 Good: 17263 Bad: 0 Port 3: link w/ 1 Good: 17264 Bad: 0 Port 4: no link Good: 0 Bad: 2984 DRAM test: Iteration: 1 Good: 0 Bad: 0 B/W: nan Gbps SRAM test: Iteration: 1 Good: 0 Bad: 0 B/W: nan Gbps SATA Test Disabled DMA test: Iteration(one pkt write, read, compare): 40 Good: 40 Bad: 0 (BQ(B Quit 07566 Bad: 207569 Bad: 107570 Bad: 1186733210.74 Gbps34 Good: 33 Bad: 0 B/W: 4.43 Gbps88 9763 97638 97639 34442653.426766120 Good: 120 Bad: 0 28773132877332287734250193872.53100 Good: 99 Bad: 0 B/W: 4.43 Gbps66 377829 377831 377832 6592510 Good: 9 Bad: 0 B/W: 12.08 Gbps34133 Bad: 0 B/W: 4.46 Gbps2020 46792654679284467930381679312 Bad: 0 B/W: 12.88 Gbps676644 558021 558023 558025 97467545320099588 6481226648125564812741133287627332323232 738221773822367382246290802091.3366653.9 66 828319 828321 828322 1449132212799984.004040 918415891841779184187607115471332331444 1008510 Bad: 81008512 Bad: 71008514 Bad: 77647576636665888 98612109861310986109228098569998115252 1887 1887 1887 : 208155323189432431366 27880822788092278811123994431656456060 368906 368907 368909 23983565749897744 4590053459034590255700982.00531530888 5491025549103554910547156741401.364633.97272 639199 639200 639203 287414435498974.0166 7292966729297672929953031865063163038080 819392 819393 819396 31899287476463444 90949789094997909501634791515069796688 99591 99593 99595 35067932373072989292 208968992089691820896937665525406362966 179790 179792 179794 3824287779695101000 Good: 1000 Bad: 0 26988721269890926989289840760938308292 44 35998623599892035999194142013624863623.99 88 450083 450086 450088 43010454596954.001212 5401784540181254018321459117639299282 66 630274 630277 630280 46183070958626132020 720375572037837203277575271595944 44 810473 810476 810478 4934334331028 Good: 1027 Bad: 0 B/W: 4.05 Gbps88 90057179005755900535093317666626173232 90668 90672 90675 5251189839594866 3080767830807706308077344106682817512812794040 170865301708688170871656900434361603.944 2609 260969 260972 57281665194934.0088 35106413510689351071788659985222722615252 441157 441160 441164 604455919006059266 53125545312583253126130201933249949346060 621354 621357 621360 6361465532732644 7114526711455471141519918776059588 801549 801552 801556 667875101 Good: 100 Bad: 0 B/W: 11.67 Gbps939267272 91647791651591655283730325426425766 98174599817487981753399714543959583.998080 [?1049l [?1l>Caught SIGINT. Exiting... ]0;root@node1-1.sb9.orbit-lab.org: ~root@node1-1:~# ]0;root@node1-1.sb9.orbit-lab.org: ~root@node1-1:~# ]0;root@node1-1.sb9.orbit-lab.org: ~root@node1-1:~# clear ]0;root@node1-1.sb9.orbit-lab.org: ~root@node1-1:~# clear~netfpga/netfpga/projects/selftest/sw/selftest -cn Found net device: nf2c0 CPCI Information ---------------- Version: 4 (rev 1) Device (Virtex) Information --------------------------- Project directory: selftest Project name: Selftest Project description: NetFPGA selftest -- exercises all major subsystems of the board Device ID: 5 Version: 1.1.0 Built against CPCI version: 4 (rev 1) [?1049h(B[?7h(B NetFPGA selftest v1.00 alpha (BClock test: pass Reg test: pass MDIO test: pass Phy 1: rev 1 up, 1000Base-TX full Phy 2: rev 1 up, 1000Base-TX full Phy 3: rev 1 up, 1000Base-TX full Phy 4: rev 1 up, 1000Base-TX full PHY test: fail Port 1: link w/ 2 Good: 17259 Bad: 0 Port 2: link w/ 1 Good: 17261 Bad: 0 Port 3: link w/ 4 Good: 17266 Bad: 2 Port 4: link w/ 3 Good: 17267 Bad: 2 DRAM test: Iteration: 1 Good: 0 Bad: 0 B/W: nan Gbps SRAM test: Iteration: 1 Good: 0 Bad: 0 B/W: nan Gbps SATA Test Disabled DMA test: Iteration(one pkt write, read, compare): 40 Good: 40 Bad: 0 (BQ(B Quit 07570 Bad: 207572 Bad: 207578 Bad: 207579 Bad: 23210.74 Gbps34 Good: 33 Bad: 0 B/W: 4.43 Gbps88 97641 976439764397643653.426766120 Good: 120 Bad: 0 28773328773 28773 28773872.53100 Good: 99 Bad: 0 B/W: 4.43 Gbps66 377843778437783753778510 Good: 9 Bad: 0 B/W: 12.08 Gbps34133 Bad: 0 B/W: 4.46 Gbps2020 467929 467930 46793564679366312 Bad: 0 B/W: 12.88 Gbps676644 55802555580265558031 558032545320099588 648124 648125 64812986481317760.74332323.893232 73821977382216738225 7382272091.3366659566 828320 828322 828327982832982212799984.004040 91841889184207918425 9184275471332331444 1008516 Bad: 81008517 Bad: 91008523 Bad: 101008524 Bad: 1076636665888 98612998613 98619 9862098569998115252 188714101887151018872111887221323189432431366 278811 278812 27881632788183431656456060 36890613689062368912 36891365749897744 459007 459007 459044590498335315303.9588 549103454910445491096549110641400646387272 639201 639202 63920676392077435498974.0166 72929957293005729304 72930665063163038080 8193 8194681949819405987476463444 9094976909498 909502 909503515069796688 995987995997996209962032373072989292 2089692208969320896952208969625406362966 17978891797908179792 17979387779695101000 Good: 1000 Bad: 0 269890 269892 26989432698963609318308293.97 44 359986203599889359990 3599913624863629 88 4500 4500 45004450090554596954.001212 540182154018321540186 5401877639299282 66 630283 63028426302885630288670958626132020 7203782720380 720383 720383271595944 44 81048048104823810484781048484331028 Good: 1027 Bad: 0 B/W: 4.05 Gbps88 900575 900578 900580890058097666626173232 90672590674490677 906779839594866 30807703080772308077593080774318281441281273.94040 17086561708675170870 1708694336160944 260969 260971 26097430260973265194934.0088 35106673510696351071 351070985222722615252 441169 441171744117224411724919006059266 5312619531264 531265 5312643249949346060 [?1049l [?1l>]0;root@node1-1.sb9.orbit-lab.org: ~root@node1-1:~# clear ]0;root@node1-1.sb9.orbit-lab.org: ~root@node1-1:~# exit logout ]0;netfpga@node1-1: ~/netfpga/projects/selftest/srcnetfpga@node1-1:~/netfpga/projects/selftest/src$ ]0;netfpga@node1-1: ~/netfpga/projects/selftest/srcnetfpga@node1-1:~/netfpga/projects/selftest/src$ ]0;netfpga@node1-1: ~/netfpga/projects/selftest/srcnetfpga@node1-1:~/netfpga/projects/selftest/src$ ]0;netfpga@node1-1: ~/netfpga/projects/selftest/srcnetfpga@node1-1:~/netfpga/projects/selftest/src$ ]0;netfpga@node1-1: ~/netfpga/projects/selftest/srcnetfpga@node1-1:~/netfpga/projects/selftest/src$ ]0;netfpga@node1-1: ~/netfpga/projects/selftest/srcnetfpga@node1-1:~/netfpga/projects/selftest/src$ add addpart addr2line ]0;netfpga@node1-1: ~/netfpga/projects/selftest/srcnetfpga@node1-1:~/netfpga/projects/selftest/src$ add-mancat /etc/ifplugd/network network/ networks ]0;netfpga@node1-1: ~/netfpga/projects/selftest/srcnetfpga@node1-1:~/netfpga/projects/selftest/src$ cat /etc/network/i if-down.d/ if-pre-up.d/ interfaces if-post-down.d/ if-up.d/ interfaces~ ]0;netfpga@node1-1: ~/netfpga/projects/selftest/srcnetfpga@node1-1:~/netfpga/projects/selftest/src$ cat /etc/network/iman ifconfig [?1049h[?1h= IFCONFIG(8) Linux Programmer's Manual IFCONFIG(8)  NAME ifconfig - configure a network interface  SYNOPSIS ifconfig [-v] [-a] [-s] [interface] ifconfig [-v] interface [aftype] options | address ...  DESCRIPTION Ifconfig is used to configure the kernel-resident network interfaces. It is used at boot time to set up interfaces as necessary. After that, it is usually only needed when debugging or when system tuning is needed.  If no arguments are given, ifconfig displays the status of the cur‐ rently active interfaces. If a single interface argument is given, it displays the status of the given interface only; if a single -a argu‐ ment is given, it displays the status of all interfaces, even those that are down. Otherwise, it configures an interface.  Address Families If the first argument after the interface name is recognized as the  Manual page ifconfig(8) line 1 /vvllaann IFCONFIG(8) Linux Programmer's Manual IFCONFIG(8)  NAME  ifconfig - configure a network interface  SYNOPSIS  ifconfig [-v] [-a] [-s] [interface]  ifconfig [-v] interface [aftype] options | address ...  DESCRIPTION  Ifconfig is used to configure the kernel-resident network interfaces.  It is used at boot time to set up interfaces as necessary. After that,  it is usually only needed when debugging or when system tuning is  needed.   If no arguments are given, ifconfig displays the status of the cur‐  rently active interfaces. If a single interface argument is given, it  displays the status of the given interface only; if a single -a argu‐  ment is given, it displays the status of all interfaces, even those  that are down. Otherwise, it configures an interface.  Address Families  If the first argument after the interface name is recognized as the IFCONFIG(8) Linux Programmer's Manual IFCONFIG(8)  NAME  ifconfig - configure a network interface  SYNOPSIS  ifconfig [-v] [-a] [-s] [interface]  ifconfig [-v] interface [aftype] options | address ...  DESCRIPTION  Ifconfig is used to configure the kernel-resident network interfaces.  It is used at boot time to set up interfaces as necessary. After that,  it is usually only needed when debugging or when system tuning is  needed.   If no arguments are given, ifconfig displays the status of the cur‐  rently active interfaces. If a single interface argument is given, it  displays the status of the given interface only; if a single -a argu‐  ment is given, it displays the status of all interfaces, even those  that are down. Otherwise, it configures an interface.  Address Families  If the first argument after the interface name is recognized as the  Pattern not found (press RETURN) /VVLLAANN IFCONFIG(8) Linux Programmer's Manual IFCONFIG(8)  NAME  ifconfig - configure a network interface  SYNOPSIS  ifconfig [-v] [-a] [-s] [interface]  ifconfig [-v] interface [aftype] options | address ...  DESCRIPTION  Ifconfig is used to configure the kernel-resident network interfaces.  It is used at boot time to set up interfaces as necessary. After that,  it is usually only needed when debugging or when system tuning is  needed.   If no arguments are given, ifconfig displays the status of the cur‐  rently active interfaces. If a single interface argument is given, it  displays the status of the given interface only; if a single -a argu‐  ment is given, it displays the status of all interfaces, even those  that are down. Otherwise, it configures an interface.  Address Families  If the first argument after the interface name is recognized as the IFCONFIG(8) Linux Programmer's Manual IFCONFIG(8)  NAME  ifconfig - configure a network interface  SYNOPSIS  ifconfig [-v] [-a] [-s] [interface]  ifconfig [-v] interface [aftype] options | address ...  DESCRIPTION  Ifconfig is used to configure the kernel-resident network interfaces.  It is used at boot time to set up interfaces as necessary. After that,  it is usually only needed when debugging or when system tuning is  needed.   If no arguments are given, ifconfig displays the status of the cur‐  rently active interfaces. If a single interface argument is given, it  displays the status of the given interface only; if a single -a argu‐  ment is given, it displays the status of all interfaces, even those  that are down. Otherwise, it configures an interface.  Address Families  If the first argument after the interface name is recognized as the  Pattern not found (press RETURN)  Manual page ifconfig(8) line 1/185 13%  name of a supported address family, that address family is used for decoding and displaying all protocol addresses. Currently supported address families include inet (TCP/IP, default), inet6 (IPv6), ax25 (AMPR Packet Radio), ddp (Appletalk Phase 2), ipx (Novell IPX) and netrom (AMPR Packet radio).  OPTIONS -a display all interfaces which are currently available, even if down  -s display a short list (like netstat -i)  -v be more verbose for some error conditions  interface The name of the interface. This is usually a driver name fol‐ lowed by a unit number, for example eth0 for the first Ethernet interface. If your kernel supports alias interfaces, you can specify them with eth0:0 for the first alias of eth0. You can use them to assign a second address. To delete an alias inter‐ face use ifconfig eth0:0 down. Note: for every scope (i.e. same net with address/netmask combination) all aliases are deleted, if you delete the first (primary).  Manual page ifconfig(8) line 27/185 27%  up This flag causes the interface to be activated. It is implic‐ itly specified if an address is assigned to the interface.  down This flag causes the driver for this interface to be shut down.  [-]arp Enable or disable the use of the ARP protocol on this interface.  [-]promisc Enable or disable the promiscuous mode of the interface. If selected, all packets on the network will be received by the interface.  [-]allmulti Enable or disable all-multicast mode. If selected, all multi‐ cast packets on the network will be received by the interface.  metric N This parameter sets the interface metric.  mtu N This parameter sets the Maximum Transfer Unit (MTU) of an inter‐ face.   Manual page ifconfig(8) line 50/185 38%  dstaddr addr Set the remote IP address for a point-to-point link (such as PPP). This keyword is now obsolete; use the pointopoint keyword instead.  netmask addr Set the IP network mask for this interface. This value defaults to the usual class A, B or C network mask (as derived from the interface IP address), but it can be set to any value.  add addr/prefixlen Add an IPv6 address to an interface.  del addr/prefixlen Remove an IPv6 address from an interface.  tunnel aa.bb.cc.dd Create a new SIT (IPv6-in-IPv4) device, tunnelling to the given destination.  irq addr Set the interrupt line used by this device. Not all devices can dynamically change their IRQ setting.  Manual page ifconfig(8) line 73/185 49%  ESCESCOOBB   Manual page ifconfig(8) line 74/185 49%  ESCESCOOBB  io_addr addr  Manual page ifconfig(8) line 75/185 50%  ESCESCOOBB  Set the start address in I/O space for this device.  Manual page ifconfig(8) line 76/185 50%  ESCESCOOBB   Manual page ifconfig(8) line 77/185 50%  ESCESCOOBB  mem_start addr  Manual page ifconfig(8) line 78/185 51%  ESCESCOOBB  Set the start address for shared memory used by this device.  Manual page ifconfig(8) line 79/185 52%  ESCESCOOBB  Only a few devices need this.  Manual page ifconfig(8) line 80/185 52%  ESCESCOOBB   Manual page ifconfig(8) line 81/185 52%  ESCESCOOBB  media type  Manual page ifconfig(8) line 82/185 53%  ESCESCOOBB  Set the physical port or medium type to be used by the device.  Manual page ifconfig(8) line 83/185 54%  ESCESCOOBB  Not all devices can change this setting, and those that can vary  Manual page ifconfig(8) line 84/185 54%  ESCESCOOBB  in what values they support. Typical values for type are  Manual page ifconfig(8) line 85/185 55%  ESCESCOOBB  10base2 (thin Ethernet), 10baseT (twisted-pair 10Mbps Ethernet),  Manual page ifconfig(8) line 86/185 56%  ESCESCOOBB  AUI (external transceiver) and so on. The special medium type  Manual page ifconfig(8) line 87/185 57%  ESCESCOOBB  of auto can be used to tell the driver to auto-sense the media.  Manual page ifconfig(8) line 88/185 58%  ESCESCOOBB  Again, not all drivers can do this.  Manual page ifconfig(8) line 89/185 59%  ESCESCOOBB   Manual page ifconfig(8) line 90/185 59%  ESCESCOOBB  [-]broadcast [addr]  Manual page ifconfig(8) line 91/185 59%  ESCESCOOBB  If the address argument is given, set the protocol broadcast  Manual page ifconfig(8) line 92/185 60%  ESCESCOOBB  address for this interface. Otherwise, set (or clear) the  Manual page ifconfig(8) line 93/185 61%  ESCESCOOBB  IFF_BROADCAST flag for the interface.  Manual page ifconfig(8) line 94/185 62%  ESCESCOOBB   Manual page ifconfig(8) line 95/185 62%  ESCESCOOBB  [-]pointopoint [addr]  Manual page ifconfig(8) line 96/185 63%  ESCESCOOBB  This keyword enables the point-to-point mode of an interface,  Manual page ifconfig(8) line 97/185 64%  ESCESCOOBB  meaning that it is a direct link between two machines with  Manual page ifconfig(8) line 98/185 65%  ESCESCOOBB  nobody else listening on it.  Manual page ifconfig(8) line 99/185 65%  ESCESCOOBB  If the address argument is also given, set the protocol address  Manual page ifconfig(8) line 100/185 66%  ESCESCOOBB  of the other side of the link, just like the obsolete dstaddr  Manual page ifconfig(8) line 101/185 67%  ESCESCOOBB  keyword does. Otherwise, set or clear the IFF_POINTOPOINT flag  Manual page ifconfig(8) line 102/185 68%  ESCESCOOBB  for the interface.  Manual page ifconfig(8) line 103/185 68%  ESCESCOOBB   Manual page ifconfig(8) line 104/185 68%  ESCESCOOBB  hw class address  Manual page ifconfig(8) line 105/185 69%  ESCESCOOBB  Set the hardware address of this interface, if the device driver  Manual page ifconfig(8) line 106/185 70%  ESCESCOOBB  supports this operation. The keyword must be followed by the  Manual page ifconfig(8) line 107/185 71%  ESCESCOOBB  name of the hardware class and the printable ASCII equivalent of  Manual page ifconfig(8) line 108/185 72%  ESCESCOOBB  the hardware address. Hardware classes currently supported  Manual page ifconfig(8) line 109/185 72%  ESCESCOOBB  include ether (Ethernet), ax25 (AMPR AX.25), ARCnet and netrom  Manual page ifconfig(8) line 110/185 74%  ESCESCOOBB  (AMPR NET/ROM).  Manual page ifconfig(8) line 111/185 74%  ESCESCOOBB   Manual page ifconfig(8) line 112/185 74%  ESCESCOOBB  multicast  Manual page ifconfig(8) line 113/185 74%  ESCESCOOBB  Set the multicast flag on the interface. This should not nor‐  Manual page ifconfig(8) line 114/185 75%  ESCESCOOBB  mally be needed as the drivers set the flag correctly them‐  Manual page ifconfig(8) line 115/185 76%  ESCESCOOBB  selves.  Manual page ifconfig(8) line 116/185 76%  ESCESCOOBB   Manual page ifconfig(8) line 117/185 76%  ESCESCOOBB  address  Manual page ifconfig(8) line 118/185 77%  ESCESCOOBB  The IP address to be assigned to this interface.  Manual page ifconfig(8) line 119/185 77%  ESCESCOOBB   Manual page ifconfig(8) line 120/185 77%  ESCESCOOBB  txqueuelen length  Manual page ifconfig(8) line 121/185 78%  ESCESCOOBB  Set the length of the transmit queue of the device. It is useful  Manual page ifconfig(8) line 122/185 79%  ESCESCOOBB  to set this to small values for slower devices with a high  Manual page ifconfig(8) line 123/185 80%  ESCESCOOBB  latency (modem links, ISDN) to prevent fast bulk transfers from  Manual page ifconfig(8) line 124/185 80%  ESCESCOOBB  disturbing interactive traffic like telnet too much.  Manual page ifconfig(8) line 125/185 81%  ESCESCOOBB   Manual page ifconfig(8) line 126/185 81%  ESCESCOOBB NOTES  Manual page ifconfig(8) line 127/185 81%  ESCESCOOBB  Since kernel release 2.2 there are no explicit interface statistics for  Manual page ifconfig(8) line 128/185 82%  ESCESCOOBB  alias interfaces anymore. The statistics printed for the original  Manual page ifconfig(8) line 129/185 83%  ESCESCOOBB  address are shared with all alias addresses on the same device. If you  Manual page ifconfig(8) line 130/185 84%  ESCESCOOBB  want per-address statistics you should add explicit accounting rules  Manual page ifconfig(8) line 131/185 85%  ESCESCOOBB  for the address using the ipchains(8) or iptables(8) command.  Manual page ifconfig(8) line 132/185 86%  ESCESCOOBB   Manual page ifconfig(8) line 133/185 86%  ESCESCOOBB  Interrupt problems with Ethernet device drivers fail with EAGAIN (SIOC‐  Manual page ifconfig(8) line 134/185 87%  SIIFLAGS: Resource temporarily unavailable) it is most likely a inter‐ rupt conflict. See http://www.scyld.com/expert/irq-conflict.html for more information.  FILES /proc/net/socket /proc/net/dev /proc/net/if_inet6  BUGS While appletalk DDP and IPX addresses will be displayed they cannot be altered by this command.  SEE ALSO route(8), netstat(8), arp(8), rarp(8), ipchains(8), iptables(8), ifup(8), interfaces(5). http://physics.nist.gov/cuu/Units/binary.html - Prefixes for binary multiples  AUTHORS Fred N. van Kempen,  Alan Cox,  Phil Blundell,   Manual page ifconfig(8) line 157/185 98% [?1l>[?1049l]0;netfpga@node1-1: ~/netfpga/projects/selftest/srcnetfpga@node1-1:~/netfpga/projects/selftest/src$ vcioniv i /etc/network/if-c- if-down.d/ if-post-down.d/ if-pre-up.d/ if-up.d/ ]0;netfpga@node1-1: ~/netfpga/projects/selftest/srcnetfpga@node1-1:~/netfpga/projects/selftest/src$ vi /etc/network/if- if-down.d/ if-post-down.d/ if-pre-up.d/ if-up.d/ ]0;netfpga@node1-1: ~/netfpga/projects/selftest/srcnetfpga@node1-1:~/netfpga/projects/selftest/src$ vi /etc/network/if-i if-down.d/ if-pre-up.d/ interfaces if-post-down.d/ if-up.d/ interfaces~ ]0;netfpga@node1-1: ~/netfpga/projects/selftest/srcnetfpga@node1-1:~/netfpga/projects/selftest/src$ vi /etc/network/iinterfaces [?1049h[?1h=[?12;25h[?12l[?25h[?25l"/etc/network/interfaces" [readonly] 10L, 274C[>c# This file describes the network interfaces available on your system # and how to activate them. For more information, see interfaces(5). # The loopback network interface auto lo iface lo inet loopback # The primary network interface auto control iface control inet dhcp ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 1,1All[?12l[?25hP+q436f\P+q6b75\P+q6b64\P+q6b72\P+q6b6c\P+q2332\P+q2334\P+q2569\P+q2a37\P+q6b31\P+q6b32\[?25l# This file describes the network interfaces available on your system # and how to activate them. For more information, see interfaces(5). # The loopback network interface auto lo iface lo inet loopback # The primary network interface auto control iface control inet dhcp ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 1,1All "/etc/network/interfaces" [readonly] 10L, 274C1,1All[?12l[?25hP+q6b33\[?25l[?12l[?25hP+q6b34\P+q6b35\P+q6b36\P+q6b37\P+q6b38\P+q6b39\P+q6b3b\P+q4631\P+q4632\P+q2531\P+q2638\P+q6b62\P+q6b49\P+q6b44\P+q6b68\P+q4037\P+q6b50\P+q6b4e\P+q4b31\P+q4b33\P+q4b34\P+q4b35\P+q6b42\[?25l2[?12l[?25h[?25l3,0-1[?12l[?25h[?25l4,1 [?12l[?25h[?25l5[?12l[?25h[?25l6[?12l[?25h[?25l7,0-1[?12l[?25h[?25l8,1 [?12l[?25h[?25l9[?12l[?25h[?25l10,1[?12l[?25h[?25l:[?12l[?25hq[?25l[?12l[?25h [?25l[?1l>[?12l[?25h[?1049l]0;netfpga@node1-1: ~/netfpga/projects/selftest/srcnetfpga@node1-1:~/netfpga/projects/selftest/src$ man 5 interfaces [?1049h[?1h= INTERFACES(5) File formats INTERFACES(5)  NAME /etc/network/interfaces - network interface configuration for ifup and ifdown  DESCRIPTION /etc/network/interfaces contains network interface configuration infor‐ mation for the ifup(8) and ifdown(8) commands. This is where you con‐ figure how your system is connected to the network.  Lines starting with `#' are ignored. Note that end-of-line comments are NOT supported, comments must be on a line of their own.  A line may be extended across multiple lines by making the last charac‐ ter a backslash.  The file consists of zero or more "iface", "mapping", "auto" and "allow-" stanzas. Here is an example. auto lo eth0 allow-hotplug eth1  iface lo inet loopback  Manual page interfaces(5) line 1  mapping eth0 script /usr/local/sbin/map-scheme map HOME eth0-home map WORK eth0-work  iface eth0-home inet static address 192.168.1.1 netmask 255.255.255.0 up flush-mail  iface eth0-work inet dhcp  iface eth1 inet dhcp Lines beginning with the word "auto" are used to identify the physical interfaces to be brought up when ifup is run with the -a option. (This option is used by the system boot scripts.) Physical interface names should follow the word "auto" on the same line. There can be multiple "auto" stanzas. ifup brings the named interfaces up in the order listed.  Lines beginning with "allow-" are used to identify interfaces that should be brought up automatically by various subsytems. This may be  Manual page interfaces(5) line 26  ESCESCOOBB  done using a command such as "ifup --allow=hotplug eth0 eth1", which  Manual page interfaces(5) line 27  ESCESCOOBB  will only bring up eth0 or eth1 if it is listed in an "allow-hotplug"  Manual page interfaces(5) line 28  ESCESCOOBB  line. Note that "allow-auto" and "auto" are synonyms.  Manual page interfaces(5) line 29  ESCESCOOBB   Manual page interfaces(5) line 30  ESCESCOOBB  Stanzas beginning with the word "mapping" are used to determine how a  Manual page interfaces(5) line 31  ESCESCOOBB  logical interface name is chosen for a physical interface that is to be  Manual page interfaces(5) line 32  ESCESCOOBB  brought up. The first line of a mapping stanza consists of the word  Manual page interfaces(5) line 33  ESCESCOOBB  "mapping" followed by a pattern in shell glob syntax. Each mapping  Manual page interfaces(5) line 34  ESCESCOOBB  stanza must contain a script definition. The named script is run with  Manual page interfaces(5) line 35  ESCESCOOBB  the physical interface name as its argument and with the contents of  Manual page interfaces(5) line 36  ESCESCOOBB  all following "map" lines (without the leading "map") in the stanza  Manual page interfaces(5) line 37  ESCESCOOBB  provided to it on its standard input. The script must print a string on  Manual page interfaces(5) line 38  ESCESCOOBB  its standard output before exiting. See /usr/share/doc/ifupdown/exam‐  Manual page interfaces(5) line 39  ESCESCOOBB  ples for examples of what the script must print.  Manual page interfaces(5) line 40  ESCESCOOBB   Manual page interfaces(5) line 41  ESCESCOOBB  Mapping a name consists of searching the remaining mapping patterns and  Manual page interfaces(5) line 42  ESCESCOOBB  running the script corresponding to the first match; the script outputs  Manual page interfaces(5) line 43  ESCESCOOBB  the name to which the original is mapped.  Manual page interfaces(5) line 44  ESCESCOOBB   Manual page interfaces(5) line 45  ESCESCOOBB  ifup is normally given a physical interface name as its first  Manual page interfaces(5) line 46  ESCESCOOBB  non-option argument. ifup also uses this name as the initial logical  Manual page interfaces(5) line 47  ESCESCOOBB  name for the interface unless it is accompanied by a suffix of the  Manual page interfaces(5) line 48  ESCESCOOBB  form =LOGICAL, in which case ifup chooses LOGICAL as the initial logi‐  Manual page interfaces(5) line 49  ESCESCOOBB  cal name for the interface. It then maps this name, possibly more than  Manual page interfaces(5) line 50  ESCESCOOBB  once according to successive mapping specifications, until no further  Manual page interfaces(5) line 51  ESCESCOOBB  mappings are possible. If the resulting name is the name of some  Manual page interfaces(5) line 52  ESCESCOOBB  defined logical interface then ifup attempts to bring up the physical  Manual page interfaces(5) line 53  ESCESCOOBB  interface as that logical interface. Otherwise ifup exits with an  Manual page interfaces(5) line 54  ESCESCOOBB  error.  Manual page interfaces(5) line 55  ESCESCOOBB   Manual page interfaces(5) line 56  ESCESCOOBB  Stanzas defining logical interfaces start with a line consisting of the  Manual page interfaces(5) line 57  ESCESCOOBB  word "iface" followed by the name of the logical interface. In simple  Manual page interfaces(5) line 58  ESCESCOOBB  configurations without mapping stanzas this name should simply be the  Manual page interfaces(5) line 59  ESCESCOOBB  name of the physical interface to which it is to be applied. (The  Manual page interfaces(5) line 60  ESCESCOOBB  default mapping script is, in effect, the echo command.) The interface  Manual page interfaces(5) line 61  ESCESCOOBB  name is followed by the name of the address family that the interface  Manual page interfaces(5) line 62  ESCESCOOBB  uses. This will be "inet" for TCP/IP networking, but there is also  Manual page interfaces(5) line 63  ESCESCOOBB  some support for IPX networking ("ipx"), and IPv6 networking ("inet6").  Manual page interfaces(5) line 64  ESCESCOOBB  Following that is the name of the method used to configure the inter‐  Manual page interfaces(5) line 65  ESCESCOOBB  face.  Manual page interfaces(5) line 66  ESCESCOOBB   Manual page interfaces(5) line 67  ESCESCOOBB  Additional options can be given on subsequent lines in the stanza.  Manual page interfaces(5) line 68  ESCESCOOBB  Which options are available depends on the family and method, as  Manual page interfaces(5) line 69  ESCESCOOBB  described below. Additional options can be made available by other  Manual page interfaces(5) line 70  ESCESCOOBB  Debian packages. For example, the wireless-tools package makes avail‐  Manual page interfaces(5) line 71  ESCESCOOBB  able a number of options prefixed with "wireless-" which can be used to  Manual page interfaces(5) line 72  ESCESCOOBB  configure the interface using iwconfig(8). (See wireless(7) for  Manual page interfaces(5) line 73  ESCESCOOBB  details.)  Manual page interfaces(5) line 74  ESCESCOOBB   Manual page interfaces(5) line 75  ESCESCOOBB  Options are usually indented for clarity (as in the example above) but  Manual page interfaces(5) line 76  ESCESCOOBB  are not required to be.  Manual page interfaces(5) line 77  ESCESCOOBB   Manual page interfaces(5) line 78  ESCESCOOBB IFACE OPTIONS  Manual page interfaces(5) line 79  ESCESCOOBB  The following "command" options are available for every family and  Manual page interfaces(5) line 80  ESCESCOOBB  method. Each of these options can be given multiple times in a single  Manual page interfaces(5) line 81  ESCESCOOBB  stanza, in which case the commands are executed in the order in which  Manual page interfaces(5) line 82  ESCESCOOBB  they appear in the stanza. (You can ensure a command never fails by  Manual page interfaces(5) line 83  ESCESCOOBB  suffixing "|| true".)  Manual page interfaces(5) line 84  ESCESCOOBB   Manual page interfaces(5) line 85  ESCESCOOBB  pre-up command  Manual page interfaces(5) line 86  ESCESCOOBB  Run command before bringing the interface up. If this command  Manual page interfaces(5) line 87  ESCESCOOBB  fails then ifup aborts, refraining from marking the interface as  Manual page interfaces(5) line 88  ESCESCOOBB  configured, prints an error message, and exits with status 0.  Manual page interfaces(5) line 89  ESCESCOOBB  This behavior may change in the future.  Manual page interfaces(5) line 90  ESCESCOOBB   Manual page interfaces(5) line 91  ESCESCOOBB  up command  Manual page interfaces(5) line 92  ESCESCOOBB   Manual page interfaces(5) line 93  ESCESCOOBB  post-up command  Manual page interfaces(5) line 94  ESCESCOOBB  Run command after bringing the interface up. If this command  Manual page interfaces(5) line 95  ESCESCOOBB  fails then ifup aborts, refraining from marking the interface as  Manual page interfaces(5) line 96  ESCESCOOBB  configured (even though it has really been configured), prints  Manual page interfaces(5) line 97  ESCESCOOBB  an error message, and exits with status 0. This behavior may  Manual page interfaces(5) line 98  ESCESCOOBB  change in the future.  Manual page interfaces(5) line 99  ESCESCOOBB   Manual page interfaces(5) line 100  ESCESCOOBB  down command  Manual page interfaces(5) line 101  ESCESCOOBB   Manual page interfaces(5) line 102  ESCESCOOBB  pre-down command  Manual page interfaces(5) line 103  ESCESCOOBB  Run command before taking the interface down. If this command  Manual page interfaces(5) line 104  ESCESCOOBB  fails then ifdown aborts, marks the interface as deconfigured  Manual page interfaces(5) line 105  ESCESCOOBB  (even though it has not really been deconfigured), and exits  Manual page interfaces(5) line 106  ESCESCOOBB  with status 0. This behavior may change in the future.  Manual page interfaces(5) line 107  ESCESCOOBB   Manual page interfaces(5) line 108  ESCESCOOBB  post-down command  Manual page interfaces(5) line 109  ESCESCOOBB  Run command after taking the interface down. If this command  Manual page interfaces(5) line 110  ESCESCOOBB  fails then ifdown aborts, marks the interface as deconfigured,  Manual page interfaces(5) line 111  ESCESCOOBB  and exits with status 0. This behavior may change in the  Manual page interfaces(5) line 112  ESCESCOOBB  future.  Manual page interfaces(5) line 113  ESCESCOOBB   Manual page interfaces(5) line 114  ESCESCOOBB  There exists for each of the above mentioned options a directory  Manual page interfaces(5) line 115  ESCESCOOBB  /etc/network/if-