Changes between Version 7 and Version 8 of Other/Summer/2017/FPGAEncryption


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Timestamp:
08/02/17 11:36:45 (5 months ago)
Author:
nlurski
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  • Other/Summer/2017/FPGAEncryption

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    77=== Mission  === 
    8 Designing a psuedo-language based on the BASIC programming language, in order to lower the entry point for FPGA programming. The RC5 encryption scheme (Rivest's Cypher) will be ported to an FPGA using synthesizable verilog. The benefit of this would be scalability of encryption. This motive for porting the RC5 scheme using our new language is to prove the efficacy of the new language for writing FPGA programs 
     8The purpose of this project is to lower the entry level for software engineers to get into writing synthesizable Verilog code by introducing a middle language for ease of use. By introducing a compiler that takes code written in a language based off of BASIC, and compiles it to a verilog switch block, the burden of many of the hardware constraints in FPGAs are taken off of the programmer. 
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    5556  <tr> 
    5657    <td><center><img src="http://www.orbit-lab.org/raw-attachment/wiki/Other/Summer/2016/SDRSpectrumDrone/nick.jpg" height=300></center></td> 
     58    <td><center><img src="http://www.orbit-lab.org/raw-attachment/wiki/Other/Summer/2017/FPGAEncryption/zarir.png" height=300></center></td> 
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    5961    <td align='center'><b>Nicholas Lurski</b><br>Electrical and Computer Engineering<br><br><i>Rutgers University</i></td> 
     62    <td align='center'><b>Zarir Hamza</b><br>High School<br><br><i>Middlesex County Academy for Science,<br>Mathematics and Engineering Technologies</i></td> 
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    65     <td><center><img src="http://www.orbit-lab.org/raw-attachment/wiki/Other/Summer/2017/FPGAEncryption/zarir.png" height=300></center></td> 
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    68     <td align='center'><b>Zarir Hamza</b><br>High School<br><br><i>Middlesex County Academy for Science, Mathematics and Engineering Technologies</i></td> 
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