Changes between Version 14 and Version 15 of Hardware/bDomains/cSandboxes/fSB6


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Timestamp:
05/13/13 22:52:29 (5 years ago)
Author:
seskar
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  • Hardware/bDomains/cSandboxes/fSB6

    v14 v15  
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    8  * [http://crkit.orbit-lab.org GENI Cognitive Radio (CRKit) platform]. Each of the two nodes, in addition to standard !WiFi ([wiki:Hardware/fDevices/cIntel2200 Intel 2915]) and WiMAX ([wiki:Hardware/fDevices/dIntel6250 Intel 6250]) card, has [http://crkit.orbit-lab.org CRKit] with [http://crkit.orbit-lab.org/wiki/Hardware/RFBoards/aSDR1 SDR] device attached through dedicated Ethernet interface (eth2). The CRKIT is also connected to a host machine (node) via a JTAG to USB interface. This interface is used by software in the Xilinx SDK (Impact and Xilinx Bash Shell) to program the Virtex-5 FPGA. After all the programming has been performed over JTAG, the on board Ethernet controller takes over and communication between the node and the CRKit takes place via the Gigabit Ethernet interface with UDP packets.More details on the protocol are available at [http://crkit.orbit-lab.org] ; Basic tutorial is available at [wiki:/Tutorials/CRKit ] 
     8===== CR-Kit ===== 
     9[http://crkit.orbit-lab.org GENI Cognitive Radio (CRKit) platform]. Each of the two nodes, in addition to standard !WiFi ([wiki:Hardware/fDevices/cIntel2200 Intel 2915]) and WiMAX ([wiki:Hardware/fDevices/dIntel6250 Intel 6250]) card, has [http://crkit.orbit-lab.org CRKit] with [http://crkit.orbit-lab.org/wiki/Hardware/RFBoards/aSDR1 SDR] device attached through dedicated Ethernet interface (eth2). The CRKIT is also connected to a host machine (node) via a JTAG to USB interface. This interface is used by software in the Xilinx SDK (Impact and Xilinx Bash Shell) to program the Virtex-5 FPGA. After all the programming has been performed over JTAG, the on board Ethernet controller takes over and communication between the node and the CRKit takes place via the Gigabit Ethernet interface with UDP packets.More details on the protocol are available at [http://crkit.orbit-lab.org] ; Basic tutorial is available at [wiki:/Tutorials/CRKit ] 
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    10  * WARP platform 
    11  * [wiki:Hardware/bDomains/cSandboxes/fSB6/aParallela Parallela based SDR platform] 
     11===== Parallela Platform ===== 
     12 
     13The Parallela SDR platform is a software defined radio platform based on a 16-core Epiphany processor chip developed by [http://www.adapteva.com/ Adapteva]. The Epiphany multi-core chip daughter card is hosted by the [http://zedboard.com/ Zedboard] motherboard, as shown below: 
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     15||[[Image(Parallela-Platform-BD.jpg, width=500px, link=, align=center)]] || [[Image(Parallela-Photo.jpg, width=500px, link=, align=center)]] || 
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     17GNU radio software can be executed within the Epiphany supercomputer, whereas control and IO related traffic is handled by the Zedboard Zynq dual-core ARM processor. The Zynq programmable logic section enables interfacing between the GNU Radio software and the lower level radio interfaces such as USRP.  
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     19===== WARP =====